Patents by Inventor Junji Fujino
Junji Fujino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230118890Abstract: A power module includes an insulating substrate, a heat dissipation member, and an electrode plate. An IGBT and a diode are mounted on the insulating substrate. The heat dissipation member is bonded to the insulating substrate by first solder. The electrode plate is disposed so as to overlap at least a part of the semiconductor element. The main surface of the insulating substrate is curved so as to have a shape convex toward the heat dissipation member. The first solder is thicker at the edges than at the center in a plan view. The semiconductor element is bonded to the electrode plate by second solder.Type: ApplicationFiled: March 25, 2021Publication date: April 20, 2023Applicant: Mitsubishi Electric CorporationInventors: Junji FUJINO, Michio OGAWA, Chika KAWAZOE, Fumio WADA, Satoru ISHIKAWA
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Patent number: 11631623Abstract: A lead member includes a plurality of lead terminals, and the lead terminals extend from the inside to the outside of a mold resin. Each of the lead terminals has a base portion and a tip end portion on the outside of the mold resin. The base portion is disposed on a region side having a semiconductor element and extends in a direction protruding from the mold resin. The tip end portion extends in a direction different from the base portion and is disposed on the opposite side to a region having the semiconductor element as viewed from the base portion. The length by which the base portion extends differs between a pair of lead terminals adjacent to each other, among the lead terminals. At least a surface of the base portion of each of the lead terminals is covered with a coating resin.Type: GrantFiled: September 4, 2019Date of Patent: April 18, 2023Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Takamasa Iwai, Junji Fujino, Hiroshi Kawashima
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Patent number: 11562979Abstract: A power module includes a plurality of conductive wire groups and a sealing member. The plurality of conductive wire groups each include a first bonded portion and a second bonded portion. A maximum gap between intermediate portions of a pair of conductive wire groups adjacent to each other is larger than a first gap between the first bonded portions of the pair of conductive wire groups adjacent to each other. The maximum gap between the intermediate portions of the pair of conductive wire groups adjacent to each other is larger than a second gap between the second bonded portions of the pair of conductive wire groups adjacent to each other. Therefore, the power module is improved in reliability.Type: GrantFiled: June 18, 2019Date of Patent: January 24, 2023Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Chika Matsui, Junji Fujino, Satoshi Kondo, Masao Uchigasaki
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Patent number: 11557531Abstract: A semiconductor device includes: a substrate; a semiconductor element arranged on the substrate; a plate-like member electrically connected to the semiconductor element; a first electrode formed on the semiconductor element and joined to the plate-like member with solder; a second electrode formed on the semiconductor element and spaced from the first electrode, and including a metal capable of forming an alloy with the solder; and a metal film formed on the semiconductor element and spaced from the second electrode in a region on the first electrode side as seen from the second electrode, in a two-dimensional view of the semiconductor element as seen from the plate-like member, and including a metal capable of forming an alloy with the solder.Type: GrantFiled: September 24, 2019Date of Patent: January 17, 2023Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Shohei Ogawa, Junji Fujino, Yusuke Ishiyama, Isao Oshima, Takumi Shigemoto
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Patent number: 11538728Abstract: A semiconductor package includes: an insulating substrate; a first semiconductor chip; a second semiconductor chip with a thickness smaller than a thickness of the first semiconductor chip; a heat radiation member in which a main surface located on an opposite side of an active surface of the first semiconductor chip and an active surface of the second semiconductor chip, respectively, are bonded to a lower surface; and a sealing resin having contact with at least part of a side wall of the heat radiation member without being raised over an upper surface of the heat radiation member to seal the first and second semiconductor chips on the insulating substrate, wherein in the heat radiation member, a thickness of a first bonding part to which the first semiconductor chip is bonded is smaller than a thickness of a second bonding part to which the second semiconductor chip is bonded.Type: GrantFiled: November 30, 2018Date of Patent: December 27, 2022Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Junji Fujino, Soichi Sakamoto, Katsumi Miyawaki, Hiroaki Ichinohe
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Publication number: 20220293434Abstract: A mold die includes a resin injection gate through which fluid resin serving as mold resin is injected toward a cavity, a resin reservoir to store the fluid resin flowing through the cavity, and a resin reservoir gate. The resin reservoir is provided on the side opposite to the side on which the resin injection gate is arranged with the cavity interposed. The resin reservoir gate communicatively connects the cavity and the resin reservoir. The opening cross-sectional area of the resin reservoir gate is smaller than the opening cross-sectional area of the resin injection gate.Type: ApplicationFiled: September 29, 2020Publication date: September 15, 2022Applicant: Mitsubishi Electric CorporationInventors: Takamasa IWAI, Yuichiro SUZUKI, Akitoshi SHIRAO, Akira KOSUGI, Junji FUJINO
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Publication number: 20220270941Abstract: An object is to provide a technique capable of suppressing an occurrence of a non-filled portion. A semiconductor device includes a base plate, a case, and a semiconductor element. The semiconductor element is disposed in a space of the base plate and the case. The semiconductor device includes a lead electrode. The lead electrode is connected to an upper surface of the semiconductor element in the space. The semiconductor device includes a raised portion. The raised portion is disposed on an upper surface of the lead electrode in the space. The semiconductor device includes a sealing resin. The sealing resin seals the semiconductor element and the lead electrode in the space.Type: ApplicationFiled: November 19, 2021Publication date: August 25, 2022Applicant: Mitsubishi Electric CorporationInventors: Kazuma Noda, Satoshi Kondo, Junji Fujino, Michio Ogawa
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Patent number: 11424178Abstract: A semiconductor module includes: an insulated circuit board; a semiconductor device mounted on the insulated circuit board; a printed wiring board arranged above the insulated circuit board and the semiconductor device and having a through-hole; a metal pile having a lower end bonded to an upper surface of the semiconductor device and a cylindrical portion penetrating through the through-hole and bonded to the printed wiring board; a case surrounding the insulated circuit board, the semiconductor device, the printed wiring board and the metal pile; and a sealing material sealing an inside of the case.Type: GrantFiled: April 9, 2020Date of Patent: August 23, 2022Assignee: Mitsubishi Electric CorporationInventors: Satoshi Kondo, Hidetoshi Ishibashi, Hiroshi Yoshida, Nobuhiro Asaji, Junji Fujino, Yusuke Ishiyama, Hodaka Rokubuichi
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Patent number: 11398447Abstract: A semiconductor device includes an insulating substrate formed by integrating a ceramic base plate and a cooling fin; a multiple of plate interconnection members; and a plurality of semiconductor elements. The one faces of the semiconductor elements are bonded to the ceramic base plate of the insulating substrate with a chip-bottom solder, and the other faces thereof are bonded to the plate-interconnection members with a chip-top solder so that plate interconnection members correspond respectively to the semiconductor elements. The chip-bottom solder and the chip-top solder both contain mainly Sn and 0.3-3 wt. % Ag and 0.5-1 wt. % Cu. This allows the semiconductor device to be reduced in size without impairing heat dissipation.Type: GrantFiled: November 29, 2018Date of Patent: July 26, 2022Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Shohei Ogawa, Junji Fujino, Satoru Ishikawa, Takumi Shigemoto, Yusuke Ishiyama
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Patent number: 11239123Abstract: A base plate (1) includes a fixed surface and a radiating surface which is a surface opposite to the fixed surface. An insulating substrate (3) is bonded to the fixed surface of the base plate (1). Conductive patterns (4,5) are provided on the insulating substrate (3). Semiconductor chips (7,8) are bonded to the conductive pattern (4). An Al wire (12) connects top surfaces of the semiconductor chip (8) to the conductive pattern (5). The insulating substrate (3), the conductive patterns (4 ,5), the semiconductor chips (7 to 10) and the Al wires (11 to 13) are sealed with resin (16). The base plate (1) includes a metal part (19) and a reinforcing member (20) provided in the metal part (19). A Young's modulus of the reinforcing member (20) is higher than a Youngs modulus of the metal part (19).Type: GrantFiled: August 29, 2013Date of Patent: February 1, 2022Assignee: Mitsubishi Electric CorporationInventors: Tatsuya Kawase, Noboru Miyamoto, Mikio Ishihara, Junji Fujino, Yuji Imoto, Naoki Yoshimatsu
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Patent number: 11183479Abstract: In a method for manufacturing a semiconductor device, a plurality of first provisional fixing portions are supplied on a front surface of a substrate such that the plurality of first provisional fixing portions are spaced from each other and thus dispersed. A first solder layer processed into a plate to be a first soldering portion is disposed in contact with the plurality of first provisional fixing portions. A semiconductor chip is disposed on the first solder layer. In addition a conductive member in the form of a flat plate is disposed thereon via a second provisional fixing portion and a second solder layer. A reflow process is performed to solder the substrate, the semiconductor chip and the conductive member together.Type: GrantFiled: March 29, 2018Date of Patent: November 23, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Shohei Ogawa, Junji Fujino, Isao Oshima, Satoru Ishikawa, Takumi Shigemoto
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Publication number: 20210327777Abstract: A lead member includes a plurality of lead terminals, and the lead terminals extend from the inside to the outside of a mold resin. Each of the lead terminals has a base portion and a tip end portion on the outside of the mold resin. The base portion is disposed on a region side having a semiconductor element and extends in a direction protruding from the mold resin. The tip end portion extends in a direction different from the base portion and is disposed on the opposite side to a region having the semiconductor element as viewed from the base portion. The length by which the base portion extends differs between a pair of lead terminals adjacent to each other, among the lead terminals. At least a surface of the base portion of each of the lead terminals is covered with a coating resin.Type: ApplicationFiled: September 4, 2019Publication date: October 21, 2021Applicant: Mitsubishi Electric CorporationInventors: Takamasa IWAI, Junji FUJINO, Hiroshi KAWASHIMA
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Publication number: 20210313253Abstract: A semiconductor device includes: a substrate; a semiconductor element arranged on the substrate; a plate-like member electrically connected to the semiconductor element; a first electrode formed on the semiconductor element and joined to the plate-like member with solder; a second electrode formed on the semiconductor element and spaced from the first electrode, and including a metal capable of forming an alloy with the solder; and a metal film formed on the semiconductor element and spaced from the second electrode in a region on the first electrode side as seen from the second electrode, in a two-dimensional view of the semiconductor element as seen from the plate-like member, and including a metal capable of forming an alloy with the solder.Type: ApplicationFiled: September 24, 2019Publication date: October 7, 2021Applicant: Mitsubishi Electric CorporationInventors: Shohei OGAWA, Junji FUJINO, Yusuke ISHIYAMA, Isao OSHIMA, Takumi SHIGEMOTO
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Publication number: 20210217724Abstract: A power module includes a plurality of conductive wire groups and a sealing member. The plurality of conductive wire groups each include a first bonded portion and a second bonded portion. A maximum gap between intermediate portions of a pair of conductive wire groups adjacent to each other is larger than a first gap between the first bonded portions of the pair of conductive wire groups adjacent to each other. The maximum gap between the intermediate portions of the pair of conductive wire groups adjacent to each other is larger than a second gap between the second bonded portions of the pair of conductive wire groups adjacent to each other. Therefore, the power module is improved in reliability.Type: ApplicationFiled: June 18, 2019Publication date: July 15, 2021Applicant: Mitsubishi Electric CorporationInventors: Chika MATSUI, Junji FUJINO, Satoshi KONDO, Masao UCHIGASAKI
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Publication number: 20210193611Abstract: A semiconductor device includes an insulating substrate formed by integrating a ceramic base plate and a cooling fin; a multiple of plate interconnection members; and a plurality of semiconductor elements. The one faces of the semiconductor elements are bonded to the ceramic base plate of the insulating substrate with a chip-bottom solder, and the other faces thereof are bonded to the plate-interconnection members with a chip-top solder so that plate interconnection members correspond respectively to the semiconductor elements. The chip-bottom solder and the chip-top solder both contain mainly Sn and 0.3-3 wt. % Ag and 0.5-1 wt. % Cu. This allows the semiconductor device to be reduced in size without impairing heat dissipation.Type: ApplicationFiled: November 29, 2018Publication date: June 24, 2021Applicant: Mitsubishi Electric CorporationInventors: Shohei OGAWA, Junji FUJINO, Satoru ISHIKAWA, Takumi SHIGEMOTO, Yusuke ISHIYAMA
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Publication number: 20210193546Abstract: The present invention provides a semiconductor device including an insulating layer, a conductive layer bonded to one main surface of the insulating layer, a semiconductor element arranged such that the upper surface of the semiconductor element faces a direction same as the one main surface of the insulating layer, an upper electrode provided on the upper surface of the semiconductor element, a wiring member that has one end electrically bonded to the upper electrode of the semiconductor element and has another end electrically bonded to the conductive layer, and has a hollow portion, a first sealing material, and a second sealing material, in which the first sealing material seals at least part of the semiconductor element so as to be in contact with the semiconductor element, and the second sealing material seals the wiring member so as to be in contact with the wiring member.Type: ApplicationFiled: March 9, 2021Publication date: June 24, 2021Applicant: Mitsubishi Electric CorporationInventors: Soichi SAKAMOTO, Junji FUJINO, Hiroshi KAWASHIMA, Taketoshi MAEDA
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Patent number: 11004761Abstract: The present invention provides a semiconductor device including an insulating layer, a conductive layer bonded to one main surface of the insulating layer, a semiconductor element arranged such that the upper surface of the semiconductor element faces a direction same as the one main surface of the insulating layer, an upper electrode provided on the upper surface of the semiconductor element, a wiring member that has one end electrically bonded to the upper electrode of the semiconductor element and has another end electrically bonded to the conductive layer, and has a hollow portion, a first sealing material, and a second sealing material, in which the first sealing material seals at least part of the semiconductor element so as to be in contact with the semiconductor element, and the second sealing material seals the wiring member so as to be in contact with the wiring member.Type: GrantFiled: February 28, 2018Date of Patent: May 11, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Soichi Sakamoto, Junji Fujino, Hiroshi Kawashima, Taketoshi Maeda
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Patent number: 10978366Abstract: An object is to provide a power module in which adhesion of a sealing resin is sufficient and which is highly reliable. The power module includes: an insulative board in which a pattern of a conductor layer is formed on a ceramic plate; power semiconductor elements placed on the insulative board; lead frames each in a plate shape connecting from electrodes of the power semiconductor elements to screw-fastening terminal portions; and a sealing resin portion that seals connection portions between the power semiconductor elements and the lead frames, and regions around the connection portions; wherein, in the lead frames, opening portions are formed at positions where each of the lead frames at least partly overlaps, in planar view, with a portion of the insulative board on which the conductor layer is not formed.Type: GrantFiled: April 27, 2018Date of Patent: April 13, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Junji Fujino, Yuji Imoto, Shohei Ogawa, Mikio Ishihara
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Publication number: 20210066175Abstract: A semiconductor module includes: an insulated circuit board; a semiconductor device mounted on the insulated circuit board; a printed wiring board arranged above the insulated circuit board and the semiconductor device and having a through-hole; a metal pile having a lower end bonded to an upper surface of the semiconductor device and a cylindrical portion penetrating through the through-hole and bonded to the printed wiring board; a case surrounding the insulated circuit board, the semiconductor device, the printed wiring board and the metal pile; and a sealing material sealing an inside of the case.Type: ApplicationFiled: April 9, 2020Publication date: March 4, 2021Applicant: Mitsubishi Electric CorporationInventors: Satoshi KONDO, Hidetoshi ISHIBASHI, Hiroshi YOSHIDA, Nobuhiro ASAJI, Junji FUJINO, Yusuke ISHIYAMA, Hodaka ROKUBUICHI
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Publication number: 20210057876Abstract: A semiconductor module includes a sub-mount having a front surface, a back surface, side surfaces connecting the front surface and the back surface, a semiconductor element soldered onto the front surface of the sub-mount, and a block soldered onto the back surface of the sub-mount. The semiconductor element protrudes outward beyond a first side surface of the sub-mount, a concave portion is formed on each of a second side surface and a third side surface of the sub-mount perpendicular to the first side surface, the concave portion extending from the front surface of the sub-mount toward the back surface of the sub-mount, and the concave portion is disposed to allow a projection of a collet to be held in the concave portion with the front surface of the sub-mount held by suction by the collet.Type: ApplicationFiled: March 12, 2019Publication date: February 25, 2021Applicant: Mitsubishi Electric CorporationInventors: Yutaka YONEDA, Junji FUJINO, Tadayoshi HATA, Jin SATO