Patents by Inventor Junji Nakatsuka

Junji Nakatsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7808326
    Abstract: In a PLL circuit, a voltage controlled oscillator 4 has two voltage-current conversion circuits 40 and 41 and a selection circuit 42 for selecting an output of either one of the voltage-current conversion circuits 40 and 41. The output of the voltage-current conversion circuit selected by the selection circuit 42 is inputted to a current controlled oscillator 45. The one voltage-current conversion circuit 41 has an input thereof connected to an output of a loop filter 3, while the other voltage-current conversion circuit 40 has an input thereof connected to an input terminal 8 for evaluating the oscillation characteristics of the voltage controlled oscillator 4.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: October 5, 2010
    Assignee: Panasonic Corporation
    Inventors: Kazuaki Sogawa, Masayoshi Kinoshita, Yuji Yamada, Junji Nakatsuka
  • Publication number: 20100244878
    Abstract: In a PLL which does not include a loop filter, an additional circuit for subjecting a voltage-controlled oscillator to a burn-in test with an appropriate oscillation frequency is realized by a less circuit configuration. A gate terminal of a diode-connected transistor (13) which has the same polarity as a voltage-to-current conversion transistor (11) in a voltage-controlled oscillator (10) is connected to a gate terminal of the transistor (11) through a switch (12a), and a current supply (14) is connected to a drain terminal of the transistor (13). By appropriately controlling the current value supplied from the current supply (14) and the size ratio between the transistor (11) and the transistor (13), a current required for performing a burn-in test can be supplied to a ring oscillator in the voltage-controlled oscillator (10).
    Type: Application
    Filed: December 20, 2007
    Publication date: September 30, 2010
    Inventors: Yuji Yamada, Masayoshi Kinoshita, Kazuaki Sogawa, Junji Nakatsuka
  • Publication number: 20100226411
    Abstract: Power consumption of an amplification circuit (11) for amplifying an inputted signal is switchable. A control circuit (12) switches the power consumption of the amplification circuit (11) such that data blank periods include an interval during which the power consumption of the amplification circuit (11) is smaller than during data periods.
    Type: Application
    Filed: April 18, 2007
    Publication date: September 9, 2010
    Inventors: Manabu Watanabe, Hiroshi Kimura, Junji Nakatsuka
  • Publication number: 20100182180
    Abstract: A D/A converter has a plurality of current sources (IS1, IS2, IS3-1 to IS3-63) including transistors and selects, according to a given digital signal, paths of the currents output from the current sources (IS1, IS2, IS3-1 to IS3-63), thereby converting the digital signal to an analog signal. In the D/A converter, a forward body bias voltage is applied to the back gate terminals of the transistors constituting each of the current sources (IS1, IS2, IS3-1 to IS3-63).
    Type: Application
    Filed: July 9, 2008
    Publication date: July 22, 2010
    Inventors: Heiji Ikoma, Junji Nakatsuka
  • Publication number: 20100140087
    Abstract: A biosensor includes a working electrode 101, a counter electrode 102 opposing the working electrode 101, a working electrode terminal 103 and a working electrode reference terminal 10 connected to the working electrode 101 by wires, and a counter electrode terminal 104 connected to the counter electrode 102 by a wire. By employing a structure with at least three electrodes, it is possible to assay a target substance without being influenced by the line resistance on the working electrode side.
    Type: Application
    Filed: November 13, 2009
    Publication date: June 10, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Hiroya Ueno, Junji Nakatsuka
  • Publication number: 20090295489
    Abstract: In a PLL circuit, a voltage controlled oscillator 4 has two voltage-current conversion circuits 40 and 41 and a selection circuit 42 for selecting an output of either one of the voltage-current conversion circuits 40 and 41. The output of the voltage-current conversion circuit selected by the selection circuit 42 is inputted to a current controlled oscillator 45. The one voltage-current conversion circuit 41 has an input thereof connected to an output of a loop filter 3, while the other voltage-current conversion circuit 40 has an input thereof connected to an input terminal 8 for evaluating the oscillation characteristics of the voltage controlled oscillator 4.
    Type: Application
    Filed: March 29, 2007
    Publication date: December 3, 2009
    Inventors: Kazuaki Sogawa, Masayoshi Kinoshita, Yuji Yamada, Junji Nakatsuka
  • Publication number: 20090284315
    Abstract: An operational amplifier includes, between an input and an output of an operational amplifier (an operational amplification stage) 10, a feedback capacitor 34 connected in negative feedback, a phase control circuit 100 having a resistor element (a resistor unit) 30 connected in series to the feedback capacitor 34. Load capacitors (load units) 32 are connected on the output side of the operational amplifier 10 and driven by an output signal from the operational amplifier 10. In a case that the capacitance values of the load capacitor 32 and 33 are increased and the phase margin of the operational amplifier becomes excessive in comparison with the optimum value, a resistance value RO of the resistor element 30 is increased to control the phase margin of the operational amplifier so as to fall within the optimum range, and thus accelerated settling properties are realized.
    Type: Application
    Filed: May 21, 2007
    Publication date: November 19, 2009
    Inventors: Satoshi Kobayashi, Junji Nakatsuka
  • Publication number: 20090223817
    Abstract: A biosensor includes a working electrode 101, a counter electrode 102 opposing the working electrode 101, a working electrode terminal 103 and a working electrode reference terminal 10 connected to the working electrode 101 by wires, and a counter electrode terminal 104 connected to the counter electrode 102 by a wire. By employing a structure with at least three electrodes, it is possible to assay a target substance without being influenced by the line resistance on the working electrode side.
    Type: Application
    Filed: March 6, 2009
    Publication date: September 10, 2009
    Applicant: PANASONIC CORPORATION
    Inventors: Hiroya UENO, Junji Nakatsuka
  • Publication number: 20090188792
    Abstract: A biosensor includes a working electrode 101, a counter electrode 102 opposing the working electrode 101, a working electrode terminal 103 and a working electrode reference terminal 10 connected to the working electrode 101 by wires, and a counter electrode terminal 104 connected to the counter electrode 102 by a wire. By employing a structure with at least three electrodes, it is possible to assay a target substance without being influenced by the line resistance on the working electrode side.
    Type: Application
    Filed: January 27, 2009
    Publication date: July 30, 2009
    Applicant: PANASONIC CORPORATION
    Inventors: Hiroya UENO, Junji NAKATSUKA
  • Patent number: 7540947
    Abstract: A biosensor includes a working electrode 101, a counter electrode 102 opposing the working electrode 101, a working electrode terminal 103 and a working electrode reference terminal 10 connected to the working electrode 101 by wires, and a counter electrode terminal 104 connected to the counter electrode 102 by a wire. By employing a structure with at least three electrodes, it is possible to assay a target substance without being influenced by the line resistance on the working electrode side.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: June 2, 2009
    Assignee: Panasonic Corporation
    Inventors: Hiroya Ueno, Junji Nakatsuka
  • Patent number: 7336123
    Abstract: In a chopper amplifier circuit operable at a low voltage utilizing a switched operational amplifier, a chopper modulator chopper-modulates an input signal according to a predetermined control signal, and outputs a chopper-modulated signal. An amplifier circuit constituted by the switched operational amplifier amplifies the chopper-modulated signal outputted from the chopper modulator, and outputs an amplified chopper-modulated signal. A chopper-demodulator of the switched operational amplifier chopper-demodulates the amplified chopper-modulated signal outputted from the amplifier circuit according to the control signal, and outputs a demodulated output signal as a chopper-amplified output signal from an output terminal. A chopper modulator chopper-modulates a demodulated signal outputted from the chopper demodulator according to the control signal, and outputs a chopper-modulated signal to an input terminal of the amplifier circuit.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: February 26, 2008
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Takeshi Yoshida, Atsushi Iwata, Mamoru Sasaki, Takayuki Mashimo, Yoshihiro Masui, Junji Nakatsuka
  • Publication number: 20060244521
    Abstract: In a chopper amplifier circuit operable at a low voltage utilizing a switched operational amplifier, a chopper modulator chopper-modulates an input signal according to a predetermined control signal, and outputs a chopper-modulated signal. An amplifier circuit constituted by the switched operational amplifier amplifies the chopper-modulated signal outputted from the chopper modulator, and outputs an amplified chopper-modulated signal. A chopper-demodulator of the switched operational amplifier chopper-demodulates the amplified chopper-modulated signal outputted from the amplifier circuit according to the control signal, and outputs a demodulated output signal as a chopper-amplified output signal from an output terminal. A chopper modulator chopper-modulates a demodulated signal outputted from the chopper demodulator according to the control signal, and outputs a chopper-modulated signal to an input terminal of the amplifier circuit.
    Type: Application
    Filed: March 28, 2006
    Publication date: November 2, 2006
    Inventors: Takeshi Yoshida, Atsushi Iwata, Mamoru Sasaki, Takayuki Mashimo, Yoshihiro Masui, Junji Nakatsuka
  • Publication number: 20060240540
    Abstract: A biosensor device includes a biosensor having a plurality of biosensor sections each including a working pole and a counter pole. The biosensor device further includes a singal processing circuit for measuring a current flowing from the working pole when different voltages are applied between the working poles and the counter poles of the respective biosensor sections and for specifying a concentration of a to-be-measured material from a measured current value.
    Type: Application
    Filed: December 8, 2004
    Publication date: October 26, 2006
    Inventor: Junji Nakatsuka
  • Publication number: 20040251131
    Abstract: A biosensor includes a working electrode 101, a counter electrode 102 opposing the working electrode 101, a working electrode terminal 103 and a working electrode reference terminal 10 connected to the working electrode 101 by wires, and a counter electrode terminal 104 connected to the counter electrode 102 by a wire. By employing a structure with at least three electrodes, it is possible to assay a target substance without being influenced by the line resistance on the working electrode side.
    Type: Application
    Filed: March 2, 2004
    Publication date: December 16, 2004
    Inventors: Hiroya Ueno, Junji Nakatsuka
  • Patent number: 6732334
    Abstract: In an analog MOS semiconductor device, each of a plurality of MOS transistors includes a plurality of micro-unit transistors. In this way, even if a process error occurs in a transistor, a systematic offset voltage and a random offset voltage are suppressed to low levels. The micro-unit transistor has a channel width that is obtained by dividing, by an integer, a smallest channel width among those of the plurality of MOS transistors. Each micro-unit transistor includes two small transistors connected in parallel to each other, including a shared drain located in a central position, gates located on opposite sides of the drain, and sources located respectively on the outer side of the gates, i.e., at opposite ends of the micro-unit transistor.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: May 4, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Junji Nakatsuka
  • Patent number: 6664825
    Abstract: The reset function incorporated microcomputer of the present invention, capable of suppressing a variation in reset voltage with a simple configuration, includes a reset decision section. In the reset decision section, a band gap reference circuit generates a predetermined reference voltage VA. A voltage dividing resistance generates a reset voltage VR from the reference voltage VA. A comparator compares the supply voltage VDD applied to the microcomputer with the reset voltage VR, and outputs a reset signal SR.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: December 16, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tadayoshi Ishikawa, Junji Nakatsuka, Hiroya Ueno, Yoshinobu Tokuno
  • Publication number: 20030041234
    Abstract: The reset function incorporated microcomputer of the present invention, capable of suppressing a variation in reset voltage with a simple configuration, includes a reset decision section. In the reset decision section, a band gap reference circuit generates a predetermined reference voltage VA. A voltage dividing resistance generates a reset voltage VR from the reference voltage VA. A comparator compares the supply voltage VDD applied to the microcomputer with the reset voltage VR, and outputs a reset signal SR.
    Type: Application
    Filed: July 17, 2002
    Publication date: February 27, 2003
    Applicant: Matsushita Electric Industries, Ltd.
    Inventors: Tadayoshi Ishikawa, Junji Nakatsuka, Hiroya Ueno, Yoshinobu Tokuno
  • Publication number: 20020190279
    Abstract: In an analog MOS semiconductor device, each of a plurality of MOS transistors includes a plurality of micro-unit transistors. In this way, even if a process error occurs in a transistor, a systematic offset voltage and a random offset voltage are suppressed to low levels. The micro-unit transistor has a channel width that is obtained by dividing, by an integer, a smallest channel width among those of the plurality of MOS transistors. Each micro-unit transistor includes two small transistors connected in parallel to each other, including a shared drain located in a central position, gates located on opposite sides of the drain, and sources located respectively on the outer side of the gates, i.e., at opposite ends of the micro-unit transistor.
    Type: Application
    Filed: March 27, 2002
    Publication date: December 19, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Junji Nakatsuka
  • Patent number: 6473018
    Abstract: For the realization of a unipolar analog input range, in addition to the provision of an analog input sampling circuit having an input capacitor, a charge transfer circuit, an integrator having an integrating capacitor, a comparator, and a D-type flip-flop, there is further provided a reference voltage sampling circuit for selectively adding either of a subtraction and addition voltages which are different from each other to a sampled analog input voltage in response to a delayed comparator output. The reference voltage sampling circuit has a subtraction and addition capacitors differing in capacitance value from each other.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: October 29, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroya Ueno, Junji Nakatsuka
  • Publication number: 20020133064
    Abstract: A &Dgr;&Sgr;-type analog-digital (A-D) converter is used for A-D conversion of a blood sugar level measured by a blood sugar sensor. This enables an accurate measurement result to be obtained with improved resolution. Using the measurement result of an offset voltage in a current-voltage converter enables compensation for the offset voltage. Moreover, using the measurement result of a blood sugar level obtained with a current being applied to a dummy resistor, i.e., an element that simulates electric characteristics of the blood sugar level sensor, enables compensation for variation in the measured value between individual devices resulting from manufacturing variation. As a result, a more precise blood sugar level measuring device having higher measurement accuracy can be implemented.
    Type: Application
    Filed: March 11, 2002
    Publication date: September 19, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroya Ueno, Junji Nakatsuka, Tadayoshi Ishikawa, Yoshinobu Tokuno