Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

Abstract: The copper interconnect formed by the use of a damascene technique is improved in dielectric breakdown strength (reliability). During post-CMP cleaning, alkali cleaning, deoxidizing process due to hydrogen anneal or the like and acid cleaning are carried out in the order. After the post-CMP cleaning and before forming an insulation film for a cap film, hydrogen plasma and ammonia plasma processes are carried out on the semiconductor substrate. In this manner, a copper-based buried interconnect is formed in an interlayer insulation film structured of an insulation material having a low dielectric constant.

Abstract: A barrier layer and a copper film are successively formed on a silicon oxide film including a groove for wiring in the silicon oxide film and a silicon nitride film, both formed on a semiconductor substrate. Thereafter, the barrier layer and the copper film are removed from outside of the groove for wiring, thereby forming a wiring. Tungsten is selectively or preferentially grown on the wiring to selectively form a tungsten film on the wiring. After the formation of the copper film, a treatment with hydrogen may be performed. After the formation of the wiring, the semiconductor substrate may be cleaned with a cleaning solution capable of removing a foreign matter or a contaminant metal. After the formation of the wiring, a treatment with hydrogen is carried out.

Abstract: Over a plug, a stopper insulating film made of an organic film is formed, followed by successive formation of an insulating film and a hard mask. In the presence of a patterned resist film, the hard mask is dry etched, whereby an interconnection groove pattern is transferred thereto. By ashing with oxygen plasma, the resist film is removed to form the interconnection-groove-pattern-transferred hard mask. At this time, the organic film constituting the stopper insulating film has been covered with the insulating film. Then, the insulating film, stopper insulating film and hard mask are removed to form the groove pattern of interconnection. Hydrogen annealing may be conducted after formation of the plug, or the stopper insulating film may be formed over the plug via an adhesion layer.

Abstract: Cu interconnections embedded in an interconnection slot of a silicon oxide film are formed by polishing using CMP to improve the insulation breakdown resistance of a copper interconnection formed using the Damascene method, and after a post-CMP cleaning step, the surface of the silicon oxide film and Cu interconnections is treated by a reducing plasma (ammonia plasma). Subsequently, a continuous cap film (silicon nitride film) is formed without vacuum break.

Abstract: In a semiconductor integrated circuit wherein an interlayer insulating film is formed over a semiconductor substrate having a semiconductor device formed thereover; and an interconnection embedded in an interconnection groove in the interlayer insulating film is formed by the deposition of a metal film such as copper and polishing by the CMP method, another interlayer insulating film over the interconnection and interlayer insulating film is formed to have a blocking film, a planarizing film and an insulating film. As the planarizing film, a film having fluidity such as SOG is employed.