Patents by Inventor Junji Noguchi

Junji Noguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060183317
    Abstract: Provided are a semiconductor device comprising a semiconductor substrate, a first insulating film formed thereover, interconnects formed over the first insulating film and having copper as a main component, a second insulating film formed over the upper surface and side surfaces of each of the interconnects and over the first insulating film and having a function of suppressing or preventing copper diffusion, and a third insulating film formed over the second insulating film and having a dielectric constant lower than that of the second insulating film; and a method of manufacturing the semiconductor device. This invention makes it possible to improve dielectric breakdown strength between copper interconnects and reduce capacitance between the copper interconnects.
    Type: Application
    Filed: April 11, 2006
    Publication date: August 17, 2006
    Inventors: Junji Noguchi, Tsuyoshi Fujiwara
  • Patent number: 7084063
    Abstract: The copper interconnect formed by the use of a damascene technique is improved in dielectric breakdown strength (reliability). During post-CMP cleaning, alkali cleaning, a deoxidizing process due to hydrogen annealing or the like, and acid cleaning are carried out in this order. After the post-CMP cleaning and before forming an insulation film for a cap film, hydrogen plasma and ammonia plasma processes are carried out on the semiconductor substrate. In this way, a copper-based buried interconnect is formed in an interlayer insulation film structured of an insulation material having a low dielectric constant.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: August 1, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Junji Noguchi, Shoji Asaka, Nobuhiro Konishi, Naohumi Ohashi, Hiroyuki Maruyama
  • Publication number: 20060141792
    Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP). method, a process for manufacturing. a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.
    Type: Application
    Filed: February 21, 2006
    Publication date: June 29, 2006
    Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
  • Patent number: 7053487
    Abstract: A semiconductor device has first interlayer insulating film having a wiring trench; a wiring portion having a first barrier metal layer formed over side walls and bottom surface of the wiring trench, a first conductor layer formed over the first barrier metal layer to embed the wiring trench, and a capping barrier metal film formed over the first conductor layer; second interlayer insulating film formed over the first interlayer insulating film and having a connecting hole; and a connecting portion having a second barrier metal layer formed over side walls and bottom surface of the connecting hole, and a second conductor layer formed over the second barrier metal layer to embed the connecting hole; wherein, at a joint between the connecting portion and wiring portion, at least one of the second barrier metal layer and capping barrier metal film on the bottom surface of the connecting hole is removed.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: May 30, 2006
    Assignee: RenesasTechnology Corp.
    Inventors: Tatsuyuki Saito, Naofumi Ohashi, Toshinori Imai, Junji Noguchi, Tsuyoshi Tamaru
  • Patent number: 7042095
    Abstract: Provided are a semiconductor device comprising a semiconductor substrate, a first insulating film formed thereover, interconnects formed over the first insulating film and having copper as a main component, a second insulating film formed over the upper surface and side surfaces of each of the interconnects and over the first insulating film and having a function of suppressing or preventing copper diffusion, and a third insulating film formed over the second insulating film and having a dielectric constant lower than that of the second insulating film; and a method of manufacturing the semiconductor device. This invention makes it possible to improve dielectric breakdown strength between copper interconnects and reduce capacitance between the copper interconnects.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: May 9, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Junji Noguchi, Tsuyoshi Fujiwara
  • Patent number: 6982200
    Abstract: Disclosed is a method of manufacturing a semiconductor device which has reliable buried interconnects (wirings) and a reliable MIM capacitor. An interconnect and a capacitor bottom electrode are formed inside a hole made in six insulation films. Then a barrier insulation film is formed on the uppermost film (of the above six insulation films) including the interconnect and the top face of the bottom electrode. After two insulation films are formed above the barrier insulation film, a hole is made in the two insulation films and a capacitor top electrode is buried in that hole. The barrier insulation film also functions as a capacity insulation film for the capacitor. Then, after three other insulation films are formed on the upper film (of the above two insulation films) including the top face of the top electrode, a hole is made in the barrier insulation film, the two insulation films, and the three other insulation films, and another interconnect is buried in that hole.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: January 3, 2006
    Assignee: Renesas Technology Corporation
    Inventors: Junji Noguchi, Toshinori Imai, Tsuyoshi Fujiwara
  • Publication number: 20050196954
    Abstract: Provided is a manufacturing method of a semiconductor device which comprises (a) depositing a first insulating film over a wafer, (b) forming an interconnect opening in the first insulating film, (c) forming, in the interconnect opening, an interconnect having a conductor film comprised mainly of copper, (d) forming a taper at a corner of said conductor film on the opening side of the interconnect opening, and (e) depositing a second insulating film over the first insulating film and interconnect. The present invention makes it possible to improve dielectric breakdown strength between interconnects each having a main conductor film comprised mainly of copper.
    Type: Application
    Filed: April 28, 2005
    Publication date: September 8, 2005
    Inventor: Junji Noguchi
  • Publication number: 20050151264
    Abstract: In a fabrication process of a semiconductor integrated circuit device, upon effecting connection of an interconnection made of aluminum or aluminum alloy and another interconnection made of Cu or Cu alloy, a barrier conductor film or plug is disposed at the joint portion between these interconnections. Among the interconnection layers formed, the uppermost one is made of a wiring material such as aluminum or aluminum alloy, while the lower one is made of Cu or Cu alloy. The lowest interconnection is made of a conductive material other than Cu or Cu alloy. For example, the conductive material which permits minute processing and has both low resistance and high EM resistance such as tungsten is employed.
    Type: Application
    Filed: February 16, 2005
    Publication date: July 14, 2005
    Inventors: Tatsuyuki Saito, Junji Noguchi, Hizuru Yamaguchi, Nobuo Owada
  • Patent number: 6908847
    Abstract: A semiconductor device has first interlayer insulating film having a wiring trench; a wiring portion having a first barrier metal layer formed over side walls and bottom surface of the wiring trench, a first conductor layer formed over the first barrier metal layer to embed the wiring trench, and a capping barrier metal film formed over the first conductor layer; second interlayer insulating film formed over the first interlayer insulating film and having a connecting hole; and a connecting portion having a second barrier metal layer formed over side walls and bottom surface of the connecting hole, and a second conductor layer formed over the second barrier metal layer to embed the connecting hole; wherein, at a joint between the connecting portion and wiring portion, at least one of the second barrier metal layer and capping barrier metal film on the bottom surface of the connecting hole is removed.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: June 21, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Tatsuyuki Saito, Naofumi Ohashi, Toshinori Imai, Junji Noguchi, Tsuyoshi Tamaru
  • Publication number: 20050118809
    Abstract: The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming wiring trenches. That is, after forming an alumina mask on an interlayer insulator composed of a low-k SiOC film via a cap insulator, the cap insulator and the interlayer insulator are dry-etched with using a photoresist film as a mask to form via holes. Next, after removing the photoresist film, the inside of the via holes are cleaned by using dilute hydrofluoric acid solution to remove alumina residue. Thereafter, the cap insulator and the interlayer insulator are dry-etched with using the alumina mask as a mask to form wiring trenches.
    Type: Application
    Filed: November 5, 2004
    Publication date: June 2, 2005
    Inventors: Junji Noguchi, Hideo Aoki, Shoji Hotta, Takayuki Oshima
  • Patent number: 6890846
    Abstract: Provided is a manufacturing method of a semiconductor device which comprises (a) depositing a first insulating film over a wafer, (b) forming an interconnect opening in the first insulating film, (c) forming, in the interconnect opening, an interconnect having a conductor film comprised mainly of copper, (d) forming a taper at a corner of said conductor film on the opening side of the interconnect opening, and (e) depositing a second insulating film over the first insulating film and interconnect. The present invention makes it possible to improve dielectric breakdown strength between interconnects each having a main conductor film comprised mainly of copper.
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: May 10, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Junji Noguchi
  • Publication number: 20050095844
    Abstract: A barrier layer and a copper film are successively formed on a silicon oxide film including a groove for wiring in the silicon oxide film and a silicon nitride film, both formed on a semiconductor substrate. Thereafter, the barrier layer and the copper film are removed from outside of the groove for wiring, thereby forming a wiring. Tungsten is selectively or preferentially grown on the wiring to selectively form a tungsten film on the wiring. After the formation of the copper film, a treatment with hydrogen may be performed. After the formation of the wiring, the semiconductor substrate may be cleaned with a cleaning solution capable of removing a foreign matter or a contaminant metal. After the formation of the wiring, a treatment with hydrogen is carried out.
    Type: Application
    Filed: October 22, 2004
    Publication date: May 5, 2005
    Inventors: Tatsuyuki Saito, Naohumi Ohashi, Toshinori Imai, Junji Noguchi, Tsuyoshi Tamaru
  • Patent number: 6864169
    Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: March 8, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Junji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hizuru Yamaguchii, Nobuo Owada
  • Patent number: 6861756
    Abstract: In a semiconductor integrated circuit device, upon connection of an interconnection made of aluminum or aluminum alloy and another interconnection made of Cu or Cu alloy, a barrier conductor film or plug is disposed at the joint portion between these interconnections. Among the interconnection layers, the uppermost one is made of a wiring material such as aluminum or aluminum alloy, while the lower, one is made of Cu or Cu alloy. The lowest interconnection is made of a conductive material other than Cu or Cu alloy. For example, the conductive material which permits minute processing and has both low resistance and high EM resistance such as tungsten is employed.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: March 1, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Tatsuyuki Saito, Junji Noguchi, Hizuru Yamaguchi, Nobuo Owada
  • Patent number: 6849535
    Abstract: A semiconductor device comprises a semiconductor substrate; a first insulating film overlying a surface of the semiconductor substrate, an upper surface of the first insulating film being nitrided; a first copper-embedded interconnection embedded in the first insulating film, and which first copper-embedded interconnection contains copper as a main component; a copper nitride film overlying an upper surface of the first copper-embedded interconnection; a cap insulating film overlying an upper surface of the first insulating film and an upper surface of the copper nitride film; and a second insulting film overlying the cap insulating film.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: February 1, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Junji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hizuru Yamaguchi, Nobuo Owada
  • Publication number: 20040227242
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Application
    Filed: March 24, 2004
    Publication date: November 18, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
  • Patent number: 6818546
    Abstract: A barrier layer and a copper film are successively formed on a silicon oxide film including a groove for wiring in the silicon oxide film and a silicon nitride film, both formed on a semiconductor substrate. Thereafter, the barrier layer and the copper film are removed from outside of the groove for wiring, thereby forming a wiring. Tungsten is selectively or preferentially grown on the wiring to selectively form a tungsten film on the wiring. After the formation of the copper film, a treatment with hydrogen may be performed. After the formation of the wiring, the semiconductor substrate may be cleaned with a cleaning solution capable of removing a foreign matter or a contaminant metal. After the formation of the wiring, a treatment with hydrogen is carried out.
    Type: Grant
    Filed: May 8, 2001
    Date of Patent: November 16, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Tatsuyuki Saito, Naohumi Ohashi, Toshinori Imai, Junji Noguchi, Tsuyoshi Tamaru
  • Patent number: 6815330
    Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: November 9, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Junji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hizuru Yamaguchii, Nobuo Owada
  • Patent number: 6800557
    Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: October 5, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
  • Patent number: 6797606
    Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: September 28, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Junji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hizuru Yamaguchii, Nobuo Owada