Patents by Inventor Junji Ogawa
Junji Ogawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960771Abstract: A first controller manages first mapping information for accessing data stored in a storage area, management of which is assigned to the first controller, and second mapping information for accessing data stored in a predetermined storage area, management of which is assigned to a second controller. The second controller, when having executed garbage collection on the predetermined storage area, changes mapping information to post-migration mapping information for accessing data after being migrated by the garbage collection.Type: GrantFiled: September 1, 2022Date of Patent: April 16, 2024Assignee: HITACHI, LTD.Inventors: Shugo Ogawa, Ryosuke Tatsumi, Yoshinori Ohira, Hiroto Ebara, Junji Ogawa
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Publication number: 20240109869Abstract: Disclosed is a charge transfer complex capable of obtaining a curable resin composition having an excellent balance between curability and storage stability when used as an epoxy-resin curing agent. The charge transfer complex has an imidazole moiety as an electron donor moiety. The charge transfer complex may be an assembly wherein electrons included in a compound (a) having an imidazole moiety are accepted by a compound (b) having an electron acceptor moiety, or may be a compound having an imidazole moiety and an electron acceptor moiety in its molecule, and the electron acceptor moiety accepts electrons included in the imidazole moiety.Type: ApplicationFiled: January 25, 2022Publication date: April 4, 2024Inventors: Takeshi ENDO, Yasuyuki MORI, Ippei OKANO, Ryo OGAWA, Junji UEYAMA
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Publication number: 20230297249Abstract: Instead of blocking a storage device low in performance of I/O processing due to execution of restoration processing along with occurrence of a failure of a non-volatile storage element, the storage device is kept used. A storage system comprises storage devices and a storage controller. The storage devices each include a plurality of non-volatile storage elements. The storage devices each is configured to: receive an I/O command from the storage controller; and transmit, when one of the storage devices detects a failure in one of the plurality of non-volatile storage elements that provides a storage area specified by the I/O command as an access destination, a response including a delay occurrence potential notification to the storage controller, the delay occurrence potential notification indicating that, although a possibility of delay in I/O processing exists, continued use of the one of the plurality of storage devices is possible.Type: ApplicationFiled: March 10, 2023Publication date: September 21, 2023Applicant: Hitachi Information & Telecommunications Engineering, Ltd.Inventors: Tomohiro MIYABE, Toshiaki Hayano, Junji Ogawa, Hiroshi Otsuru
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Patent number: 11714751Abstract: In a complex system including; one or more storage systems including a cache and a storage controller; and one or more storage boxes including a storage medium, the storage box generates redundant data from write data received from a server, and writes the write data and the redundant data to the storage medium. The storage box transmits the write data to the storage system when it is difficult to generate the redundant data or it is difficult to write the write data and the redundant data to the storage medium. The storage system stores the received write data in the cache.Type: GrantFiled: January 20, 2022Date of Patent: August 1, 2023Assignee: HITACHI, LTD.Inventors: Akira Yamamoto, Ryosuke Tatsumi, Yoshinori Ohira, Junji Ogawa
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Publication number: 20230185489Abstract: A first controller manages first mapping information for accessing data stored in a storage area, management of which is assigned to the first controller, and second mapping information for accessing data stored in a predetermined storage area, management of which is assigned to a second controller. The second controller, when having executed garbage collection on the predetermined storage area, changes mapping information to post-migration mapping information for accessing data after being migrated by the garbage collection.Type: ApplicationFiled: September 1, 2022Publication date: June 15, 2023Applicant: Hitachi, Ltd.Inventors: Shugo OGAWA, Ryosuke TATSUMI, Yoshinori OHIRA, Hiroto EBARA, Junji OGAWA
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Patent number: 11675545Abstract: One or a plurality of physical storage devices that provide a physical storage area are connected to first and second computers. The computer updates metadata indicating the address correspondence relationship between the logical address of the volume and the physical address of the physical storage area in the write processing performed based on a write request designating the volume. The first computer copies the metadata to the second computer while receiving the write request. When the address correspondence relationship indicated by the copied metadata portion is changed during copying of the metadata, the first computer updates the metadata portion and copies the metadata portion to the second computer.Type: GrantFiled: September 14, 2021Date of Patent: June 13, 2023Assignee: Hitachi, Ltd.Inventors: Shugo Ogawa, Akira Yamamoto, Yoshinori Ohira, Ryosuke Tatsumi, Junji Ogawa, Hiroto Ebara
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Publication number: 20220334726Abstract: One or a plurality of physical storage devices that provide a physical storage area are connected to first and second computers. The computer updates metadata indicating the address correspondence relationship between the logical address of the volume and the physical address of the physical storage area in the write processing performed based on a write request designating the volume. The first computer copies the metadata to the second computer while receiving the write request. When the address correspondence relationship indicated by the copied metadata portion is changed during copying of the metadata, the first computer updates the metadata portion and copies the metadata portion to the second computer.Type: ApplicationFiled: September 14, 2021Publication date: October 20, 2022Applicant: Hitachi, Ltd.Inventors: Shugo Ogawa, Akira Yamamoto, Yoshinori Ohira, Ryosuke Tatsumi, Junji Ogawa, Hiroto Ebara
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Publication number: 20220147456Abstract: In a complex system including; one or more storage systems including a cache and a storage controller; and one or more storage boxes including a storage medium, the storage box generates redundant data from write data received from a server, and writes the write data and the redundant data to the storage medium. The storage box transmits the write data to the storage system when it is difficult to generate the redundant data or it is difficult to write the write data and the redundant data to the storage medium. The storage system stores the received write data in the cache.Type: ApplicationFiled: January 20, 2022Publication date: May 12, 2022Inventors: Akira YAMAMOTO, Ryosuke TATSUMI, Yoshinori OHIRA, Junji OGAWA
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Patent number: 11237962Abstract: In a complex system including; one or more storage systems including a cache and a storage controller; and one or more storage boxes including a storage medium, the storage box generates redundant data from write data received from a server, and writes the write data and the redundant data to the storage medium. The storage box transmits the write data to the storage system when it is difficult to generate the redundant data or it is difficult to write the write data and the redundant data to the storage medium. The storage system stores the received write data in the cache.Type: GrantFiled: September 11, 2020Date of Patent: February 1, 2022Assignee: HITACHI, LTD.Inventors: Akira Yamamoto, Ryosuke Tatsumi, Yoshinori Ohira, Junji Ogawa
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Patent number: 11210214Abstract: A storage system including a storage controller for compressing a data from a host and a plurality of nonvolatile memory drives for writing the compressed data. The storage controller provides the host with a first logical address space as a logical storage area and includes a plurality of first physical address spaces corresponding to the first logical address space and manages storage areas of the plurality of nonvolatile memory drives. Each of the plurality of nonvolatile memory drives includes a second physical address space that manages a physical storage area of the nonvolatile memory and a second logical address space that corresponds to the second physical address space and to each of the plurality of first physical address spaces. The second logical address spaces and the first logical address space are managed with a common size and a common management size, and leading addresses are aligned with the management size.Type: GrantFiled: September 13, 2019Date of Patent: December 28, 2021Assignees: HITACHI, LTD., HITACHI INFORMATION & TELECOMMUNICATION ENGINEERING LTD.Inventors: Junji Ogawa, Shigeo Homma
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Publication number: 20210294742Abstract: In a complex system including; one or more storage systems including a cache and a storage controller; and one or more storage boxes including a storage medium, the storage box generates redundant data from write data received from a server, and writes the write data and the redundant data to the storage medium. The storage box transmits the write data to the storage system when it is difficult to generate the redundant data or it is difficult to write the write data and the redundant data to the storage medium. The storage system stores the received write data in the cache.Type: ApplicationFiled: September 11, 2020Publication date: September 23, 2021Inventors: Akira YAMAMOTO, Ryosuke TATSUMI, Yoshinori OHIRA, Junji OGAWA
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Patent number: 11068180Abstract: A higher-level system that inputs and outputs data to/from a storage area including one or more logical areas respectively provided from one or more NVM drives manages the storage area, and manages a plurality of chunks that are a plurality of areas forming the storage area, each of the chunks being a unit of data input/output and being an non-overwritable area. Each of the plurality of chunks has the same chunk size, and each of the plurality of chunks includes a part of each of one or more logical areas. Each of the plurality of chunks includes, for each of the one or more NVM drives, all or part of one or more logical blocks that are one or more ranges corresponding to one or more physical blocks, respectively, but does not include at least a part of a logical block that is entirely or partially included in another chunk.Type: GrantFiled: September 9, 2019Date of Patent: July 20, 2021Assignee: HITACHI, LTD.Inventors: Yukihiro Yoshino, Junji Ogawa, Go Uehara
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Patent number: 10915441Abstract: An upper system of an NVM device transmits, to the NVM device, a write command that designates a logical address, the write command being associated with an expiration date corresponding to a data expiration date correlated with write target data. The NVM device correlates an expiration date correlated with the write command with a logical address specified from the write command. The NVM device writes pieces of data of which the remaining time which is the time to an expiration date belongs to the same remaining time range to the same physical storage area among the plurality of physical storage areas. The NVM device erases data from a physical storage area when the expiration dates of all pieces of data in the physical storage area have expired.Type: GrantFiled: August 23, 2017Date of Patent: February 9, 2021Assignees: HITACHI, LTD., HITACHI INFORMATION & TELECOMMUNICATION ENGINEERING LTD.Inventors: Koshi Hoshino, Shigeo Homma, Junji Ogawa, Yoshinori Ohira
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Patent number: 10860225Abstract: An information processing apparatus includes a memory and a processor and accesses a first storage device and a second storage device wherein an access speed of the second storage device is higher than an access speed of the first storage device. The memory stores information relating to a request in a request from the information processing apparatus to the second storage device. The processor, which is connected to the memory, determines a load on the second storage device based on the information relating to the request.Type: GrantFiled: March 19, 2018Date of Patent: December 8, 2020Assignee: FUJITSU LIMITEDInventors: Satoshi Kazama, Shinya Kuwamura, Eiji Yoshida, Junji Ogawa
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Patent number: 10803972Abstract: A flash memory module includes a flash memory and a controller. The controller acquires information indicating reliability of monitoring target data of the flash memory, specifies a first cell, which is a cell having a threshold voltage level lower than a threshold voltage level of a corresponding cell in expected value data obtained by correcting an error bit of the monitoring target data, among cells in which error bits have occurred of the monitoring target data when it is determined that the reliability indicated by the acquired information is lower than a predetermined condition, and transmits rewrite correction target cell data, which is data corresponding to data of the first cell in the expected value data, to the flash memory. The flash memory injects an electron into the first cell based on a threshold voltage indicated by the rewrite correction target cell data.Type: GrantFiled: March 6, 2017Date of Patent: October 13, 2020Assignee: Hitachi, Ltd.Inventors: Akifumi Suzuki, Junji Ogawa
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Publication number: 20200264971Abstract: A storage system including a storage controller for compressing a data from a host and a plurality of nonvolatile memory drives for writing the compressed data. The storage controller provides the host with a first logical address space as a logical storage area and includes a plurality of first physical address spaces corresponding to the first logical address space and manages storage areas of the plurality of nonvolatile memory drives. Each of the plurality of nonvolatile memory drives includes a second physical address space that manages a physical storage area of the nonvolatile memory and a second logical address space that corresponds to the second physical address space and to each of the plurality of first physical address spaces. The second logical address spaces and the first logical address space are managed with a common size and a common management size, and leading addresses are aligned with the management size.Type: ApplicationFiled: September 13, 2019Publication date: August 20, 2020Applicants: HITACHI, LTD., HITACHI INFORMATION & TELECOMMUNICATION ENGINEERING, LTD.Inventors: Junji OGAWA, Shigeo HOMMA
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Publication number: 20200192573Abstract: A higher-level system that inputs and outputs data to/from a storage area including one or more logical areas respectively provided from one or more NVM drives manages the storage area, and manages a plurality of chunks that are a plurality of areas forming the storage area, each of the chunks being a unit of data input/output and being an non-overwritable area. Each of the plurality of chunks has the same chunk size, and each of the plurality of chunks includes a part of each of one or more logical areas. Each of the plurality of chunks includes, for each of the one or more NVM drives, all or part of one or more logical blocks that are one or more ranges corresponding to one or more physical blocks, respectively, but does not include at least a part of a logical block that is entirely or partially included in another chunk.Type: ApplicationFiled: September 9, 2019Publication date: June 18, 2020Applicant: HITACHI, LTD.Inventors: Yukihiro YOSHINO, Junji OGAWA, Go UEHARA
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Patent number: 10684785Abstract: A storage system according to one aspect of the present invention includes a plurality of storage devices using flash memory as a storage medium. The flash memory used for the storage device may include flash memory configured to operate each cell as a cell capable of storing n-bit information or a cell capable of storing m-bit information (where n<m). The storage system may periodically acquire a number of remaining erasures from the storage device and predict the lifetime of the storage device by using the acquired number of remaining erasures and the storage device operation time. If the predicted lifetime is less than a predetermined value (service life) a predetermined number of cells may be changed to cells capable of storing n-bit information.Type: GrantFiled: February 23, 2017Date of Patent: June 16, 2020Assignee: Hitachi, Ltd.Inventors: Yoshihiko Fujii, Shigeo Homma, Junji Ogawa, Yoshinori Ohira
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Patent number: 10614014Abstract: To increase the number of selectable chips without adding a signal line to a general purpose memory controller. A semiconductor storage device includes a memory controller, a plurality of memory chips, a selection unit which is connected to the memory controller and is connected with the plurality of memory chips to be able to select any one of the plurality of memory chips, and a switch unit which is connected to the memory controller and the selection unit. The memory controller and the selection unit are connected by a signal line for transmitting a first signal outputted from the memory controller and configured to select the memory chips. The memory controller and the switch unit are connected by a signal line for transmitting a second signal outputted from the memory controller and configured to select the memory chips.Type: GrantFiled: September 26, 2016Date of Patent: April 7, 2020Assignee: Hitachi, Ltd.Inventors: Yasuhiro Ikeda, Yutaka Uematsu, Shungo Okabe, Akihiro Inamura, Takahiko Iwasaki, Junji Ogawa
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Publication number: 20200097396Abstract: An upper system of an NVM device transmits, to the NVM device, a write command that designates a logical address, the write command being associated with an expiration date corresponding to a data expiration date correlated with write target data. The NVM device correlates an expiration date correlated with the write command with a logical address specified from the write command. The NVM device writes pieces of data of which the remaining time which is the time to an expiration date belongs to the same remaining time range to the same physical storage area among the plurality of physical storage areas. The NVM device erases data from a physical storage area when the expiration dates of all pieces of data in the physical storage area have expired.Type: ApplicationFiled: August 23, 2017Publication date: March 26, 2020Applicants: HITACHI, LTD., HITACHI INFORMATION & TELECOMMUNICATION ENGINEERING, LTD.Inventors: Koshi HOSHINO, Shigeo HOMMA, Junji OGAWA, Yoshinori OHIRA