Patents by Inventor Junji Ogawa
Junji Ogawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160011938Abstract: In a storage apparatus including a storage medium including a plurality of pages as a unit of reading and writing data, a first data block including a data block received from a higher-level device is generated, a second data block of a predetermined size including one or more undivided first data blocks is generated, a third data block in which a correction code is added to the second data block is generated, the third data block is stored in a page buffer, and one or more of the third data blocks stored in the page buffer is written in a page, which is a write destination, out of the pages of the storage medium.Type: ApplicationFiled: August 30, 2013Publication date: January 14, 2016Applicant: Hitachi, Ltd.Inventors: Hideyuki KOSEKI, Takashi TSUNEHIRO, Junji OGAWA, Nagamasa MIZUSHIMA, Atsushi KAWAMURA
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Patent number: 9223655Abstract: Provided is a storage system which allows reliability to be improved by recovering target data relatively early. A plurality of storage apparatuses 210 forms a parity group 230 for data recovery. An FM board 150 serving as a first memory apparatus is a large-capacity memory apparatus with a parity calculation function 1512. In carrying out a data recovery process, the FM board 150 acquires other data D0 and D1 and a parity P0 needed to recover target data D2, and carries out a predetermined parity calculation by the parity calculation function to recover the target data D2. When the recovered data D2 is written to a plurality of different FM boards 150, the data D2 becomes redundant and the data recovery process is therefore considered to be complete.Type: GrantFiled: July 26, 2013Date of Patent: December 29, 2015Assignee: HITACHI, LTD.Inventors: Sadahiro Sugimoto, Junji Ogawa
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Publication number: 20150370488Abstract: An example of the invention is a memory device including a controller and a plurality of randomly accessible memories that are capable of storing user data from a host. The controller includes data management information managing correspondence relations between address areas to be designated by the host and the plurality of memories, and compression policy management information managing associations of the address areas to be designated by the host with priorities in compressing user data to be stored in the plurality of memories. The controller is configured to determine a compression policy associated with a designated address area included in an access request from the host based on a priority associated with the designated address area and information on free space of the plurality of memories.Type: ApplicationFiled: May 22, 2013Publication date: December 24, 2015Inventors: Satoru WATANABE, Junji OGAWA, Nagamasa MIZUSHIMA
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Publication number: 20150324294Abstract: A cache memory comprises a cache controller and a nonvolatile semiconductor memory as a storage medium. The nonvolatile semiconductor memory comprises multiple blocks, which are data erase units, and each block comprises multiple pages, which are data write and read units. The cache controller receives data and attribute information of the data, and, based on the received attribute information and attribute information of the data stored in the multiple blocks, selects a storage-destination block for storing the received data, and writes the received data to a page inside the selected storage-destination block.Type: ApplicationFiled: January 31, 2013Publication date: November 12, 2015Applicant: Hitachi, Ltd.Inventors: JUNJI OGAWA, Akifumi Suzuki
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Patent number: 9183136Abstract: A storage control apparatus comprises a storage unit, an association unit, and an execution unit. The storage unit stores association information showing multiple physical chunks which are configured in a physical address space of a nonvolatile semiconductor memory, multiple logical storage areas which are configured in a logical address space of the nonvolatile semiconductor memory, multiple logical chunks which are respectively associated with the multiple physical chunks, and an association between a logical storage area and a logical chunk. The association unit changes the association by changing the association information in accordance with a state of the nonvolatile semiconductor memory, and identifies based on the association information a physical storage area corresponding to a logical storage area specified in an input/output request from a computer. The execution unit executes the input/output request with respect to the identified physical storage area.Type: GrantFiled: May 16, 2012Date of Patent: November 10, 2015Assignee: Hitachi, Ltd.Inventors: Atsushi Kawamura, Junji Ogawa
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Publication number: 20150317097Abstract: Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. A storage apparatus comprising a flash memory control device equipped with one or more flash memory modules, wherein the flash memory module comprises at least one flash memory chip for providing a storage area, and a controller for controlling writing/reading of data including user data and a guarantee code accompanying the user data to and from the storage area provided by the flash memory chip, wherein the controller respectively divides a plurality of the data having the common user data into the user data and the guarantee code, stores one of the user data in an area of a predetermined unit of the storage area, and links and stores each of the guarantee codes accompanying the plurality of user data in an area of a predetermined unit of the storage area.Type: ApplicationFiled: July 14, 2015Publication date: November 5, 2015Applicant: HITACHI, LTD.Inventors: Atsushi KAWAMURA, Junji OGAWA
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Patent number: 9164693Abstract: A first storage system comprises a first RAID group comprising multiple first storage devices, which constitute the basis of a first logical volume. A second storage system comprises a second RAID group comprising multiple second storage devices, which constitute the basis of a second logical volume. The RAID configuration of the first RAID group and the RAID configuration of the second RAID group are the same, and the type of a compression/decompression function of the respective first storage devices and the type of a compression/decompression function of the respective second storage devices are the same. Compressed data is read from a first storage device without being decompressed with respect to the data inside a first logical volume, and the read compressed data is written to a second storage device, which is in the same location in RAID in the second RAID group as the location in RAID of this first storage device.Type: GrantFiled: May 13, 2014Date of Patent: October 20, 2015Assignee: HITACHI, LTD.Inventors: Junichi Hara, Junji Ogawa
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Publication number: 20150254016Abstract: Storage system comprises a second storage apparatus, which is coupled to multiple first storage apparatuses and is of a different type from the first storage apparatuses, and a first control device, which exists either inside or outside of the second storage apparatus. Row of stripes comprising multiple data elements obtained by segmenting a prescribed data unit, and a redundancy code for rebuilding the data elements, is distributively stored in multiple first storage apparatuses, which are more numerous than the total number of stripe data elements, which are either the data elements or redundancy code, in the row of stripes. The row of stripes is configured to enable the rebuilding of the stripe data elements even when a failure has occurred in up to a prescribed allowable number, which is two or more, of the first storage apparatuses storing the stripe data elements of the relevant row of stripes.Type: ApplicationFiled: May 26, 2015Publication date: September 10, 2015Applicant: Hitachi, Ltd.Inventors: HIROAKI AKUTSU, Junji Ogawa
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Patent number: 9128847Abstract: A cache control apparatus comprises a primary cache part, a secondary cache part for caching data destaged from the primary cache part, and a controller connected to the primary cache part and to the secondary cache part. The secondary cache part has a first storage part and a second storage part having a lifetime longer than that of the first storage part. The controller determines whether the data destaged from the primary cache part is to be stored in the first storage part or the second storage part in the secondary cache part, based on a use state indicating whether or not the data has been updated, and stores the data in the first storage part or the second storage part determined.Type: GrantFiled: October 18, 2012Date of Patent: September 8, 2015Assignee: Hitachi, Ltd.Inventors: Yuji Ito, Junji Ogawa, Hideyuki Koseki
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Patent number: 9111618Abstract: Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. A flash memory module includes a plurality of flash memory chips and a memory controller. Each flash memory chip includes a plurality of blocks, each block including a plurality of physical pages, each physical page being a unit for writing/reading data. The memory controller is configured to manage a first set and a second set of user data and a guarantee code associated with the user data. If the first set and the second set of user data are the same, then the same data sets are stored in a first physical page and the first and second guarantee codes are stored in a second physical page.Type: GrantFiled: July 11, 2014Date of Patent: August 18, 2015Assignee: HITACHI, LTD.Inventors: Atsushi Kawamura, Junji Ogawa
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Publication number: 20150197094Abstract: An object is to prevent the occurrence of contact failure between a cartridge equipped with a recording medium and an ink jet recording apparatus. A bottle body is crushed to reduce the volume thereof when an ink or solvent is sucked out of the bottle body. A bottle has a neck and a mouth. The neck is rigid. The ROM unit records therein an ink or solvent type, a serial number, the capacity of the bottle, and the amount of remaining ink or solvent. The ROM unit has first and second arms, and freely movably attached to the neck by the first and second arms. A positioning hole is formed on a ROM holder body which houses therein a recording medium. The positioning hole positions the ROM holder body in cooperation with a positioning pin of a reservoir.Type: ApplicationFiled: December 4, 2014Publication date: July 16, 2015Applicant: KEYENCE CORPORATIONInventors: Junji Ogawa, Hiroki Wada, Mamoru Idaka
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Publication number: 20150186063Abstract: A shared device unit, which comprises a storage device, is coupled to a plurality of storage systems. The shared device unit provides a plurality of storage areas, which are based on the storage device, to the plurality of storage systems. Each storage system stores allocation management information which comprises an ID of a storage area provided to thereof among the plurality of storage areas, and provides the storage area corresponded to the ID included in the allocation management information to the host computer coupled thereto among the plurality of host computers.Type: ApplicationFiled: March 11, 2015Publication date: July 2, 2015Applicant: Hitachi, Ltd.Inventors: Miho Imazaki, Shigeo Homma, Hiroaki Akutsu, Yoshiaki Eguchi, Akira Yamamoto, Junji Ogawa
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Patent number: 9063663Abstract: The flash memory controller compresses data in response to a write request. On condition that there is a compression effect with respect to the compressed data, the flash memory controller writes the compressed data to the base area of a physical block of a flash memory. As physical pages assigned to the physical block, the flash memory controller reduces the physical pages assigned to the base area from 102 down to 59, and increases the physical pages assigned to the update area from 26 up to 69. Therefore, it is possible to suppress exhaustion of physical pages which are assigned to the update area, to reduce the number of erases of the physical block, and to consequently prolong device operating life.Type: GrantFiled: September 21, 2010Date of Patent: June 23, 2015Assignee: Hitachi, Ltd.Inventors: Akifumi Suzuki, Atsushi Kawamura, Junji Ogawa
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Publication number: 20150153957Abstract: A storage system, which comprises multiple memory cells and a storage controller, wherein the storage controller manages cell mode information, which either directly or indirectly denotes the number of bits to be stored in multiple memory cells. The cell mode information can be changed in accordance with a request from a management system.Type: ApplicationFiled: February 5, 2015Publication date: June 4, 2015Inventors: Tsukasa SHIBAYAMA, Akifumi SUZUKI, Nobuhiro MAKI, Junji OGAWA, Masayasu ASANO
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Publication number: 20150154075Abstract: Provided is a storage system which allows reliability to be improved by recovering target data relatively early. A plurality of storage apparatuses 210 forms a parity group 230 for data recovery. An FM board 150 serving as a first memory apparatus is a large-capacity memory apparatus with a parity calculation function 1512. In carrying out a data recovery process, the FM board 150 acquires other data D0 and D1 and a parity P0 needed to recover target data D2, and carries out a predetermined parity calculation by the parity calculation function to recover the target data D2. When the recovered data D2 is written to a plurality of different FM boards 150, the data D2 becomes redundant and the data recovery process is therefore considered to be complete.Type: ApplicationFiled: July 26, 2013Publication date: June 4, 2015Applicant: HITACHI, LTD.Inventors: Sadahiro Sugimoto, Junji Ogawa
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Patent number: 9047220Abstract: Storage system comprises a second storage apparatus, which is coupled to multiple first storage apparatuses and is of a different type from the first storage apparatuses, and a first control device, which exists either inside or outside of the second storage apparatus. Row of stripes comprising multiple data elements obtained by segmenting a prescribed data unit, and a redundancy code for rebuilding the data elements, is distributively stored in multiple first storage apparatuses, which are more numerous than the total number of stripe data elements, which are either the data elements or redundancy code, in the row of stripes. The row of stripes is configured to enable the rebuilding of the stripe data elements even when a failure has occurred in up to a prescribed allowable number, which is two or more, of the first storage apparatuses storing the stripe data elements of the relevant row of stripes.Type: GrantFiled: July 23, 2012Date of Patent: June 2, 2015Assignee: Hitachi, Ltd.Inventors: Hiroaki Akutsu, Junji Ogawa
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Publication number: 20150127896Abstract: A storage system comprises a storage comprising a nonvolatile storage medium, and a storage control apparatus for inputting/outputting data to/from the storage. The storage control apparatus comprises a memory for storing management information, which is information used in inputting/outputting data to/from the storage, and a control part for controlling access to the storage. The control part stores the management information, which is stored in the memory, in the storage as a base image, and when the management information is updated subsequent to the base image being stored in the storage, creates a journal comprising information related to this update, and stores the journal in the storage as a journal group which is configured from multiple journals.Type: ApplicationFiled: January 15, 2015Publication date: May 7, 2015Applicant: HITACHI, LTD.Inventors: Atsushi KAWAMURA, Junji OGAWA
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Publication number: 20150106555Abstract: A nonvolatile semiconductor storage system has multiple nonvolatile semiconductor storage media, a control circuit having a media interface group (one or more interface devices) coupled to the multiple nonvolatile semiconductor storage media, and multiple switches. The media interface group and the multiple switches are coupled via data buses, and each switch and each of two or more nonvolatile chips are coupled via a data bus. The switch is configured so as to switch a coupling between a data bus coupled to the media interface group and a data bus coupled to any of multiple nonvolatile chips that are coupled to this switch. The control circuit partitions write-target data into multiple data elements, switches a coupling by controlling the multiple switches, and distributively sends the multiple data elements to multiple nonvolatile chips.Type: ApplicationFiled: December 17, 2014Publication date: April 16, 2015Applicant: Hitachi, Ltd.Inventors: ATSUSHI ISHIKAWA, Koji Sonoda, Go Uehara, Junji Ogawa, Hideyuki Koseki
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Patent number: 9003087Abstract: A shared device unit, which comprises a storage device, is coupled to a plurality of storage systems. The shared device unit provides a plurality of storage areas, which are based on the storage device, to the plurality of storage systems. Each storage system stores allocation management information which comprises an ID of a storage area provided to thereof among the plurality of storage areas, and provides the storage area corresponded to the ID included in the allocation management information to the host computer coupled thereto among the plurality of host computers.Type: GrantFiled: March 18, 2013Date of Patent: April 7, 2015Assignee: Hitachi, Ltd.Inventors: Miho Imazaki, Shigeo Homma, Hiroaki Akutsu, Yoshiaki Eguchi, Akira Yamamoto, Junji Ogawa
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Patent number: 8984211Abstract: A storage system, which comprises multiple memory cells and a storage controller, wherein the storage controller manages cell mode information, which either directly or indirectly denotes the number of bits to be stored in multiple memory cells. The cell mode information can be changed in accordance with a request from a management system.Type: GrantFiled: December 21, 2011Date of Patent: March 17, 2015Assignee: Hitachi, Ltd.Inventors: Tsukasa Shibayama, Akifumi Suzuki, Nobuhiro Maki, Junji Ogawa, Masayasu Asano