Patents by Inventor Junji Oh
Junji Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11778818Abstract: An alternating stack of insulating layers and electrically conductive layers, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, and memory stack structures extending through the alternating stack are formed over a substrate. A patterned etch mask layer including discrete openings is formed thereabove. Via cavities through an upper region of the retro-stepped dielectric material portion by performing a first anisotropic etch process. Metal plates are selectively formed on physically exposed surfaces of a first subset of the electrically conductive layers by a selective metal deposition process. A subset of the via cavities without any metal plates therein are vertically extended downward by performing a second anisotropic etch process while the metal plates protect underlying electrically conductive layers. Via cavities can be formed without punching through electrically conductive layers.Type: GrantFiled: July 21, 2020Date of Patent: October 3, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Ryo Mochizuki, Yasuo Kasagi, Michiaki Sano, Junji Oh, Yujin Terasawa, Hiroaki Namba
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Publication number: 20220028879Abstract: An alternating stack of insulating layers and electrically conductive layers, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, and memory stack structures extending through the alternating stack are formed over a substrate. A patterned etch mask layer including discrete openings is formed thereabove. Via cavities through an upper region of the retro-stepped dielectric material portion by performing a first anisotropic etch process. Metal plates are selectively formed on physically exposed surfaces of a first subset of the electrically conductive layers by a selective metal deposition process. A subset of the via cavities without any metal plates therein are vertically extended downward by performing a second anisotropic etch process while the metal plates protect underlying electrically conductive layers. Via cavities can be formed without punching through electrically conductive layers.Type: ApplicationFiled: July 21, 2020Publication date: January 27, 2022Inventors: Ryo MOCHIZUKI, Yasuo KASAGI, Michiaki SANO, Junji OH, Yujin TERASAWA, Hiroaki NAMBA
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Patent number: 11101284Abstract: A method of forming a semiconductor structure includes providing a dopant species selected from carbon, boron, nitrogen or oxygen into an upper portion of a semiconductor region to form a doped etch stop semiconductor material portion over a remaining semiconductor material portion, forming an overlying material portion over the etch stop semiconductor material portion, etching through the overlying material portion by an etch process that removes the overlying material portion selective to a material of the etch stop semiconductor material portion, and depositing at least one fill material over the etch stop semiconductor material portion.Type: GrantFiled: December 18, 2018Date of Patent: August 24, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Jayavel Pachamuthu, Hiroyuki Kinoshita, Masaaki Higashitani, Makoto Dei, Junji Oh
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Publication number: 20200194450Abstract: A method of forming a semiconductor structure includes providing a dopant species selected from carbon, boron, nitrogen or oxygen into an upper portion of a semiconductor region to form a doped etch stop semiconductor material portion over a remaining semiconductor material portion, forming an overlying material portion over the etch stop semiconductor material portion, etching through the overlying material portion by an etch process that removes the overlying material portion selective to a material of the etch stop semiconductor material portion, and depositing at least one fill material over the etch stop semiconductor material portion.Type: ApplicationFiled: December 18, 2018Publication date: June 18, 2020Inventors: Jayavel Pachamuthu, Hiroyuki Kinoshita, Masaaki Higashitani, Makoto Dei, Junji Oh
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Publication number: 20180342531Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack containing a memory array region and a terrace region. Memory stack structures containing a memory film and a vertical semiconductor channel extend through the memory array region of the alternating stack. Support pillar structures extending through the terrace region of the alternating stack. The support pillar structures have different heights from each other.Type: ApplicationFiled: May 29, 2017Publication date: November 29, 2018Inventors: Hiromasa Susuki, Masanori Tsutsumi, Shigehisa Inoue, Junji Oh, Kensuke Yamaguchi, Seiji Shimabukuro, Yuji Fukano, Ryoichi Ehara, Youko Furihata
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Patent number: 10141331Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack containing a memory array region and a terrace region. Memory stack structures containing a memory film and a vertical semiconductor channel extend through the memory array region of the alternating stack. Support pillar structures extending through the terrace region of the alternating stack. The support pillar structures have different heights from each other.Type: GrantFiled: May 29, 2017Date of Patent: November 27, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Hiromasa Susuki, Masanori Tsutsumi, Shigehisa Inoue, Junji Oh, Kensuke Yamaguchi, Seiji Shimabukuro, Yuji Fukano, Ryoichi Ehara, Youko Furihata
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Publication number: 20170125430Abstract: A switching field effect transistor and the memory devices can be formed employing a same set of processing steps. An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures for memory devices and gate dielectric-channel structures for the field effect transistor can be simultaneously formed in a memory region and in a transistor region, respectively. After replacement of the sacrificial material layers with electrically conductive layers, portions of the electrically conductive layers in a memory region are electrically isolated from one another to provide independently controlled control gate electrodes for the memory devices, while portions of the electrically conductive layers in the transistor region are electrically shorted among one another to provide a single gate electrode for the switching field effect transistor.Type: ApplicationFiled: October 28, 2015Publication date: May 4, 2017Inventors: Masatoshi NISHIKAWA, Hiroaki KOKETSU, Fumiaki TOYAMA, Junji OH
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Patent number: 9620512Abstract: A switching field effect transistor and the memory devices can be formed employing a same set of processing steps. An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures for memory devices and gate dielectric-channel structures for the field effect transistor can be simultaneously formed in a memory region and in a transistor region, respectively. After replacement of the sacrificial material layers with electrically conductive layers, portions of the electrically conductive layers in a memory region are electrically isolated from one another to provide independently controlled control gate electrodes for the memory devices, while portions of the electrically conductive layers in the transistor region are electrically shorted among one another to provide a single gate electrode for the switching field effect transistor.Type: GrantFiled: October 28, 2015Date of Patent: April 11, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Masatoshi Nishikawa, Hiroaki Koketsu, Fumiaki Toyama, Junji Oh
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Patent number: 9117675Abstract: A semiconductor device production method includes: forming a protection film on a semiconductor substrate; forming a first resist pattern on the protection film; implanting a first impurity ion into the semiconductor substrate using the first resist pattern as a mask; removing the first resist pattern; forming on the surface of the semiconductor substrate a chemical reaction layer that takes in surface atoms from the semiconductor substrate through chemical reaction, after the removing of the first resist pattern; removing the chemical reaction layer formed on the semiconductor substrate and removing the surface of the semiconductor substrate, after the forming of the chemical reaction layer; and growing a semiconductor layer epitaxially on the surface of the semiconductor substrate, after the removing of the surface of the semiconductor substrate.Type: GrantFiled: August 13, 2013Date of Patent: August 25, 2015Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Junji Oh, Masanori Terahara
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Patent number: 9105743Abstract: The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate electrode formed above the first epitaxial layer with a first gate insulating film formed therebetween and first source/drain regions, and a second transistor including a second impurity layer containing boron and carbon, or arsenic or antimony, a second epitaxial layer formed above the second impurity layer, a second gate electrode formed above the second epitaxial layer with a second gate insulating film thinner than the first gate insulating film formed therebetween, and second source/drain regions.Type: GrantFiled: April 30, 2014Date of Patent: August 11, 2015Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Taiji Ema, Kazushi Fujita, Junji Oh
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Publication number: 20140235022Abstract: The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate electrode formed above the first epitaxial layer with a first gate insulating film formed therebetween and first source/drain regions, and a second transistor including a second impurity layer containing boron and carbon, or arsenic or antimony, a second epitaxial layer formed above the second impurity layer, a second gate electrode formed above the second epitaxial layer with a second gate insulating film thinner than the first gate insulating film formed therebetween, and second source/drain regions.Type: ApplicationFiled: April 30, 2014Publication date: August 21, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Taiji Ema, Kazushi Fujita, Junji Oh
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Patent number: 8778786Abstract: Silicon loss prevention in a substrate during transistor device element manufacture is achieved by limiting a number of photoresist mask and chemical oxide layer stripping opportunities during the fabrication process. This can be achieved through the use of a protective layer that remains on the substrate during formation and stripping of photoresist masks used in identifying the implant areas into the substrate. In addition, undesirable reworking steps due to photoresist mask misalignment are eliminated or otherwise have no effect on consuming silicon from the substrate during fabrication of device elements. In this manner, device elements with the same operating characteristics and performance can be consistently made from lot to lot.Type: GrantFiled: May 29, 2012Date of Patent: July 15, 2014Assignee: SuVolta, Inc.Inventors: Lance Scudder, Pushkar Ranade, Dalong Zhao, Teymur Bakhishev, Urupattur C. Sridharan, Taiji Ema, Toshifumi Mori, Mitsuaki Hori, Junji Oh, Kazushi Fujita, Yasunobu Torii
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Patent number: 8766369Abstract: The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate electrode formed above the first epitaxial layer with a first gate insulating film formed therebetween and first source/drain regions, and a second transistor including a second impurity layer containing boron and carbon, or arsenic or antimony, a second epitaxial layer formed above the second impurity layer, a second gate electrode formed above the second epitaxial layer with a second gate insulating film thinner than the first gate insulating film formed therebetween, and second source/drain regions.Type: GrantFiled: September 24, 2012Date of Patent: July 1, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Taiji Ema, Kazushi Fujita, Junji Oh
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Publication number: 20140057421Abstract: A semiconductor device production method includes: forming a protection film on a semiconductor substrate; forming a first resist pattern on the protection film; implanting a first impurity ion into the semiconductor substrate using the first resist pattern as a mask; removing the first resist pattern; forming on the surface of the semiconductor substrate a chemical reaction layer that takes in surface atoms from the semiconductor substrate through chemical reaction, after the removing of the first resist pattern; removing the chemical reaction layer formed on the semiconductor substrate and removing the surface of the semiconductor substrate, after the forming of the chemical reaction layer; and growing a semiconductor layer epitaxially on the surface of the semiconductor substrate, after the removing of the surface of the semiconductor substrate.Type: ApplicationFiled: August 13, 2013Publication date: February 27, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: JUNJI OH, MASANORI TERAHARA
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Patent number: 8592278Abstract: The method of manufacturing the semiconductor device includes forming a trench to be an alignment mark in a semiconductor substrate, forming a mask film exposing a region to be a device isolation region and covering a region to be a device region by aligning with the alignment mark above the semiconductor substrate with the trench formed in, anisotropically etching the semiconductor substrate with the mask film as a mask to form a device isolation trench in the region to be the device isolation region of the semiconductor substrate, and burying the device isolation trench by an insulating film to form a device isolation insulating film. In forming the trench, the trench is formed in a depth which is smaller than a depth equivalent to a thickness of the mask film.Type: GrantFiled: July 6, 2011Date of Patent: November 26, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Kazushi Fujita, Junji Oh
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Patent number: 8476124Abstract: The method of manufacturing the semiconductor device includes amorphizing a first region and a second region of a semiconductor substrate by an ion implantation, implanting a first impurity and a second impurity respectively in the first region and the second region, activating the implanted impurities to form a first impurity layer and a second impurity layer, epitaxially growing a semiconductor layer above the semiconductor substrate with the impurity layers formed on, growing a gate insulating film above the first region and the second region, and forming a first gate electrode above the gate insulating film in the first region and the second gate electrode above the gate insulating film in the second region.Type: GrantFiled: July 5, 2011Date of Patent: July 2, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Junji Oh
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Patent number: 8294217Abstract: The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate electrode formed above the first epitaxial layer with a first gate insulating film formed therebetween and first source/drain regions, and a second transistor including a second impurity layer containing boron and carbon, or arsenic or antimony, a second epitaxial layer formed above the second impurity layer, a second gate electrode formed above the second epitaxial layer with a second gate insulating film thinner than the first gate insulating film formed therebetween, and second source/drain regions.Type: GrantFiled: June 29, 2011Date of Patent: October 23, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Taiji Ema, Kazushi Fujita, Junji Oh
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Patent number: 8273630Abstract: A method for manufacturing a semiconductor device includes forming a silicon substrate having first and second surfaces, the silicon substrate including no oxide film or an oxide film having a thickness no greater than 100 nm, forming a first oxide film at least on the second surface of the silicon substrate, forming a first film by covering at least the first surface, forming a mask pattern on the first surface by patterning the first film, forming a device separating region on the first surface by using the mask pattern as a mask, forming a gate insulating film on the first surface, forming a gate electrode on the first surface via the gate insulating film, forming a source and a drain one on each side of the gate electrode, and forming a wiring layer on the silicon substrate while maintaining the first oxide film on the second surface.Type: GrantFiled: September 21, 2011Date of Patent: September 25, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Takayuki Wada, Masanori Terahara, Junji Oh
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Publication number: 20120080754Abstract: The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate electrode formed above the first epitaxial layer with a first gate insulating film formed therebetween and first source/drain regions, and a second transistor including a second impurity layer containing boron and carbon, or arsenic or antimony, a second epitaxial layer formed above the second impurity layer, a second gate electrode formed above the second epitaxial layer with a second gate insulating film thinner than the first gate insulating film formed therebetween, and second source/drain regions.Type: ApplicationFiled: June 29, 2011Publication date: April 5, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Taiji Ema, Kazushi Fujita, Junji Oh
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Publication number: 20120083082Abstract: The method of manufacturing the semiconductor device includes forming a trench to be an alignment mark in a semiconductor substrate, forming a mask film exposing a region to be a device isolation region and covering a region to be a device region by aligning with the alignment mark above the semiconductor substrate with the trench formed in, anisotropically etching the semiconductor substrate with the mask film as a mask to form a device isolation trench in the region to be the device isolation region of the semiconductor substrate, and burying the device isolation trench by an insulating film to form a device isolation insulating film. In forming the trench, the trench is formed in a depth which is smaller than a depth equivalent to a thickness of the mask film.Type: ApplicationFiled: July 6, 2011Publication date: April 5, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Kazushi Fujita, Junji Oh