Patents by Inventor Junji Oh
Junji Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120083079Abstract: The method of manufacturing the semiconductor device includes amorphizing a first region and a second region of a semiconductor substrate by an ion implantation, implanting a first impurity and a second impurity respectively in the first region and the second region, activating the implanted impurities to form a first impurity layer and a second impurity layer, epitaxially growing a semiconductor layer above the semiconductor substrate with the impurity layers formed on, growing a gate insulating film above the first region and the second region, and forming a first gate electrode above the gate insulating film in the first region and the second gate electrode above the gate insulating film in the second region.Type: ApplicationFiled: July 5, 2011Publication date: April 5, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Junji Oh
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Publication number: 20120009752Abstract: A method for manufacturing a semiconductor device includes forming a silicon substrate having first and second surfaces, the silicon substrate including no oxide film or an oxide film having a thickness no greater than 100 nm, forming a first oxide film at least on the second surface of the silicon substrate, forming a first film by covering at least the first surface, forming a mask pattern on the first surface by patterning the first film, forming a device separating region on the first surface by using the mask pattern as a mask, forming a gate insulating film on the first surface, forming a gate electrode on the first surface via the gate insulating film, forming a source and a drain one on each side of the gate electrode, and forming a wiring layer on the silicon substrate while maintaining the first oxide film on the second surface.Type: ApplicationFiled: September 21, 2011Publication date: January 12, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Takayuki Wada, Masanori Terahara, Junji Oh
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Patent number: 8043917Abstract: A method for manufacturing a semiconductor device includes forming a silicon substrate having first and second surfaces, the silicon substrate including no oxide film or an oxide film having a thickness no greater than 100 nm, forming a first oxide film at least on the second surface of the silicon substrate, forming a first film by covering at least the first surface, forming a mask pattern on the first surface by patterning the first film, forming a device separating region on the first surface by using the mask pattern as a mask, forming a gate insulating film on the first surface, forming a gate electrode on the first surface via the gate insulating film, forming a source and a drain one on each side of the gate electrode, and forming a wiring layer on the silicon substrate while maintaining the first oxide film on the second surface.Type: GrantFiled: May 19, 2009Date of Patent: October 25, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Takayuki Wada, Masanori Terahara, Junji Oh
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Patent number: 7947567Abstract: A semiconductor device fabrication method is disclosed. The method comprises an insulating film forming step of forming an insulating film on a semiconductor substrate; a trench forming step of forming a trench for device isolation in a predetermined part of the semiconductor substrate; a trench filling step of forming a buried oxide film filling the trench; a polishing step of polishing the buried oxide film on the semiconductor substrate until the insulating film is exposed; a thickness measuring step of measuring the thickness of the insulating film remaining after the polishing; an etching amount determining step of determining an etching amount of etching the polished buried oxide film based on the measured thickness of the remaining insulating film; and a buried oxide film etching step of etching the polished buried oxide film based on the determined etching amount.Type: GrantFiled: August 27, 2007Date of Patent: May 24, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Junji Oh, Masanori Terahara
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Publication number: 20090317956Abstract: A method for manufacturing a semiconductor device includes forming a silicon substrate having first and second surfaces, the silicon substrate including no oxide film or an oxide film having a thickness no greater than 100 nm, forming a first oxide film at least on the second surface of the silicon substrate, forming a first film by covering at least the first surface, forming a mask pattern on the first surface by patterning the first film, forming a device separating region on the first surface by using the mask pattern as a mask, forming a gate insulating film on the first surface, forming a gate electrode on the first surface via the gate insulating film, forming a source and a drain one on each side of the gate electrode, and forming a wiring layer on the silicon substrate while maintaining the first oxide film on the second surface.Type: ApplicationFiled: May 19, 2009Publication date: December 24, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Takayuki Wada, Masanori Terahara, Junji Oh
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Publication number: 20080081384Abstract: A semiconductor device fabrication method is disclosed. The method comprises an insulating film forming step of forming an insulating film on a semiconductor substrate; a trench forming step of forming a trench for device isolation in a predetermined part of the semiconductor substrate; a trench filling step of forming a buried oxide film filling the trench; a polishing step of polishing the buried oxide film on the semiconductor substrate until the insulating film is exposed; a thickness measuring step of measuring the thickness of the insulating film remaining after the polishing; an etching amount determining step of determining an etching amount of etching the polished buried oxide film based on the measured thickness of the remaining insulating film; and a buried oxide film etching step of etching the polished buried oxide film based on the determined etching amount.Type: ApplicationFiled: August 27, 2007Publication date: April 3, 2008Applicant: FUJITSU LIMITEDInventors: Junji OH, Masanori TERAHARA
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Patent number: 7294577Abstract: There is provided a method of manufacturing semiconductor device comprising removing an organic substance from a semiconductor surface having an oxide film thereon, the semiconductor surface being formed to have a line width of 50 nm or less; removing the oxide film from the semiconductor surface; drying the semiconductor surface without using an organic solvent; and forming a silicide layer on the semiconductor surface after drying the semiconductor surface.Type: GrantFiled: March 24, 2005Date of Patent: November 13, 2007Assignee: Fujitsu LimitedInventors: Junji Oh, Yuka Hayami, Ryou Nakamura
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Publication number: 20070093068Abstract: A semiconductor device manufacturing method involves heating up a solution containing sulfuric acid and hydrogen peroxide solution, replenishing the solution with a predetermined quantity of sulfuric acid and a predetermined quantity of hydrogen peroxide solution at a predetermined interval, maintaining a concentration of the sulfuric acid in the solution at a predetermined concentration level or higher, immersing the semiconductor substrate in the solution, and cleaning the semiconductor substrate.Type: ApplicationFiled: June 5, 2006Publication date: April 26, 2007Applicant: FUJITSU LIMITEDInventors: Junji Oh, Yuka Kase, Masatoshi Osuki, Masaomi Yamano
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Patent number: 7030026Abstract: The semiconductor device fabrication method comprises the step of forming electrodes 20 in a first element region 14n and in a second element region 14p; the step of forming a first resist film 22 which is opened in the first element region 14n; the step of forming a first dopant diffused region 28 with the first resist film 22 and the gate electrode 20 as a mask; the first ashing processing step of ashing the first resist film 22; the step of forming a sidewall insulation film 42 over the side wall of the gate electrode 20; the step of forming a second resist film 44 which is opened in the first element region 14n; the forming a second dopant diffused region 48 with the second resist film 44, the gate electrode 20 and the sidewall insulation film 42 as a mask; and the second ashing processing step for ashing the second resist film 44. The ashing processing period of time in the first ashing processing step is shorter than the ashing processing period of time in the second ashing processing step.Type: GrantFiled: October 30, 2003Date of Patent: April 18, 2006Assignee: Fujitsu LimitedInventors: Yuka Hayami, Junji Oh, Takashi Saiki, Masataka Kase
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Publication number: 20050215003Abstract: There is provided a method of manufacturing semiconductor device comprising removing an organic substance from a semiconductor surface having an oxide film thereon, the semiconductor surface being formed to have a line width of 50 nm or less; removing the oxide film from the semiconductor surface; drying the semiconductor surface without using an organic solvent; and forming a silicide layer on the semiconductor surface after drying the semiconductor surface.Type: ApplicationFiled: March 24, 2005Publication date: September 29, 2005Applicant: FUJITSU LIMITEDInventors: Junji Oh, Yuka Hayami, Ryou Nakamura
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Publication number: 20040102047Abstract: The semiconductor device fabrication method comprises the step of forming electrodes 20 in a first element region 14n and in a second element region 14p; the step of forming a first resist film 22 which is opened in the first element region 14n; the step of forming a first dopant diffused region 28 with the first resist film 22 and the gate electrode 20 as a mask; the first ashing processing step of ashing the first resist film 22; the step of forming a sidewall insulation film 42 over the side wall of the gate electrode 20; the step of forming a second resist film 44 which is opened in the first element region 14n; the forming a second dopant diffused region 48 with the second resist film 44, the gate electrode 20 and the sidewall insulation film 42 as a mask; and the second ashing processing step for ashing the second resist film 44. The ashing processing period of time in the first ashing processing step is shorter than the ashing processing period of time in the second ashing processing step.Type: ApplicationFiled: October 30, 2003Publication date: May 27, 2004Applicant: FUJITSU LIMITEDInventors: Yuka Hayami, Junji Oh, Takashi Saiki, Masataka Kase