Patents by Inventor Junji Yamada

Junji Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220415411
    Abstract: A memory system includes: a semiconductor storage device including a memory cell array that includes memory cells and a temperature counter configured to increase a count value thereof at a rate that depends on a temperature of the memory cell array; and a memory controller configured to acquire the count value from the semiconductor storage device and reserve a refresh operation for a written memory cell of the memory cell array when a cumulative value of the count value, which is accumulated from when data was written to the memory cell to when the count value is acquired, exceeds a predetermined value.
    Type: Application
    Filed: February 24, 2022
    Publication date: December 29, 2022
    Inventor: Junji YAMADA
  • Patent number: 11451446
    Abstract: A system includes a device management apparatus. The device management apparatus includes: one or more memories; and one or more processors. The one or more processors are configured to: store user group information that defines at least one user group, each user group being a group of one or more users; store device group definition information that defines at least one device group in association with at least one user group, each device group being a group of one or more network devices; store authority information of each device group associated with at least one user group; store association information that associates each of the network devices to be objects of management with at least one of the device groups; and determine whether to permit a user operation related to a network device belonging to a device group based on the authority information of each of the device groups.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: September 20, 2022
    Assignee: BUFFALO INC.
    Inventors: Atsuo Nakahata, Junji Inoue, Osamu Yamada
  • Patent number: 11422256
    Abstract: A distance measurement system includes: a signal generator which generates a light emission signal that instructs light emission and an exposure signal that instructs exposure of reflected light; a first illumination and distance measurement light source which receives the light emission signal and, according to the signal received, performs the light emission for illumination without a purpose of distance measurement and the light emission with the purpose of distance measurement using the reflected light; an imaging device which receives the exposure signal, performs the exposure according to the signal received, and obtains an amount of light exposure of the reflected light; and a calculator which calculates distance information using the amount of light exposure and outputs the distance information, wherein the distance measurement system has operation modes including an illumination mode and a first distance measurement mode.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: August 23, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Junji Ito, Tohru Yamada, Toshiya Fujii
  • Patent number: 8785252
    Abstract: A semiconductor device includes a thermoplastic resin case, a semiconductor chip mounted within the thermoplastic resin case, a metal terminal having a wire bonding surface and an opposing contact surface, and a wire connected between the wire bonding surface and the semiconductor chip. The contact surface of the metal terminal is thermoplastically bonded at an area to the inside of the thermoplastic resin case.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: July 22, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masafumi Matsumoto, Tatsuya Iwasa, Junji Yamada, Masaru Furukawa
  • Patent number: 8709871
    Abstract: A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: April 29, 2014
    Inventors: Junji Yamada, Hiroaki Ikeda, Kayoko Shibata, Yoshihiko Inoue, Hitoshi Miwa, Tatsuya Ijima
  • Publication number: 20130143365
    Abstract: A semiconductor device includes a thermoplastic resin case, a semiconductor chip mounted within the thermoplastic resin case, a metal terminal having a wire bonding surface and an opposing contact surface, and a wire connected between the wire bonding surface and the semiconductor chip. The contact surface of the metal terminal is thermoplastically bonded at an area to the inside of the thermoplastic resin case.
    Type: Application
    Filed: February 1, 2013
    Publication date: June 6, 2013
    Inventors: Masafumi MATSUMOTO, Tatsuya IWASA, Junji YAMADA, Masaru FURUKAWA
  • Patent number: 8399976
    Abstract: A semiconductor device includes a thermoplastic resin case, a semiconductor chip mounted within the thermoplastic resin case, a metal terminal having a wire bonding surface and an opposing contact surface, and a wire connected between the wire bonding surface and the semiconductor chip. The contact surface of the metal terminal is thermoplastically bonded at an area to the inside of the thermoplastic resin case.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: March 19, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masafumi Matsumoto, Tatsuya Iwasa, Junji Yamada, Masaru Furukawa
  • Publication number: 20120122251
    Abstract: A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.
    Type: Application
    Filed: November 10, 2011
    Publication date: May 17, 2012
    Applicant: Elpida Memory Inc.
    Inventors: Junji YAMADA, Hiroaki IKEDA, Kayoko SHIBATA, Yoshihiko INOUE, Hitoshi MIWA, Tatsuya IJIMA
  • Patent number: 8076764
    Abstract: A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: December 13, 2011
    Assignee: Elpida Memory Inc.
    Inventors: Junji Yamada, Hiroaki Ikeda, Kayoko Shibata, Yoshihiko Inoue, Hitoshi Miwa, Tatsuya Ijima
  • Patent number: 8014213
    Abstract: A semiconductor memory device is constituted of a plurality of fuses (or anti-fuses) used for internal voltage adjustment or timing adjustment after manufacturing, a selector for sequentially selecting the fuses, and a single-direction latch circuit for latching a fuse breakdown determination result which is produced by determining whether or not each fuse selected by the selector is broken down and which is varied in a single direction from the low level to the high level or in a single direction from the high level to the low level. The semiconductor memory device allows the fuse breakdown determination to progress with a high reliability by use of a relatively small chip area and to cope with a failure in which one or more fuses are accidentally short-circuited to an unwanted potential.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: September 6, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Junji Yamada
  • Publication number: 20110174665
    Abstract: To provide a polyester resin container with a fracturable portion that has improved openability and to provide its production method. In the polyester resin container with a fracturable portion, in which the material of the container is polyester resin, which comprises a mouth portion 20 contiguous to the container body and a fracturable portion 30 located above the mouth portion 20 integrally, which is equipped with a fracturable structure that can be opened by fracturing the boundary part between the opening end 22 of the mouth portion 20 and the fracturable portion 30; a groove 40 is formed approximately perpendicular to the outer surface of the boundary part between the opening end 22 of the mouth portion 20 and the fracturable portion 30 of the container, and the intrinsic viscosity of the polyester resin located at the periphery of the groove 40 is lowered than the intrinsic viscosity of the polyester resin located at a location other than the periphery of the groove 40.
    Type: Application
    Filed: April 27, 2007
    Publication date: July 21, 2011
    Applicant: Daiwa Can Company
    Inventors: Yoichiro Inoue, Junji Yamada
  • Patent number: 7969025
    Abstract: An electric power semiconductor device including first and second circuit patterns formed on main surfaces of first and second insulating substrates, respectively, first and second semiconductor chips mounted on the first and second circuit patterns, respectively, a multilayer electrode plate assembly disposed between the first and second insulating substrates, having first, second and third electrode terminals provided with a distance from each other, a first connecting conductor made by wire bonding for connecting the first and second semiconductor chips to the first and second electrode terminals, and a second connecting conductor having an extending portion extended from a part of the third electrode terminal to be connected to the second circuit pattern, and the connection between the extending portion of the third electrode terminal and the second circuit pattern is implemented by a solder.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: June 28, 2011
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Junji Yamada, Seiji Saiki
  • Publication number: 20110153304
    Abstract: A storage section stores a netlist representing a test object circuit. An extracting section extracts, from the netlist stored in the storage section, a subnetlist representing a periodic circuit which is included in the test object circuit and which outputs a periodic output signal corresponding to a periodic input signal. An analyzing section performs transient analysis of the periodic circuit represented by the subnetlist extracted by the extracting section, for one period of the periodic output signal outputted by the periodic circuit. A simulation section performs transient analysis of the test object circuit represented by the netlist stored in the storage section on the basis of the result of the analysis performed by the analyzing section.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 23, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Junji YAMADA
  • Patent number: 7919852
    Abstract: A semiconductor device including: an insulating substrate including a ceramic substrate having first and second principal surfaces, a first metallic conductor fixed on the first principal surface, and a second metallic conductor fixed on the second principal surface; a semiconductor element disposed on the first metallic conductor on the first principal surface; and a base plate connected to the second metallic conductor on the second principal surface, and on which the insulating substrate being disposed. The second metallic conductor includes a joint area connected to the second principal surface, and a non-joint area formed around the joint area.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: April 5, 2011
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Junji Yamada
  • Patent number: 7894293
    Abstract: In a three-dimensional stacked memory having through electrodes, no optimal layer arrangement, bank arrangement, control methods have been established, and thus optimal methods are desired to be established. A stacked memory includes memory core layers, an interposer, and an IF chip. By stacking memory core layers having the same arrangement, it is possible to cope with both of no-parity operation and parity operation. Further, bank designation irrespective of the number of stacks of the memory core layers can be achieved by assignment of a row address and a bank address. Further, the IF chip has refresh counters for performing a refresh control of the stacked memory. This arrangement provides a stacked memory including stacked memory core layers having through electrodes.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: February 22, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroaki Ikeda, Kayoko Shibata, Junji Yamada
  • Patent number: 7777325
    Abstract: A power semiconductor module comprising: a power semiconductor element; a case for receiving the power semiconductor element; a control terminal which is connected to a control electrode of the power semiconductor element, the control terminal is installed in a state of protruding from an upper surface of the case; and a conductive spring which is inserted into the control terminal so that an inner surface of the spring makes contact with at least a part of the side surface of the control terminal, the conductive spring is electrically connected to a printed substrate placed as opposed to the upper surface of the case by making pressurization contact with the printed substrate.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: August 17, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventor: Junji Yamada
  • Patent number: 7773236
    Abstract: An image forming processing circuit and an image forming apparatus having a clock stop function of the invention perform, in an image forming processing process, supply of a clock for processing only in a period in which the clock is required and stop the supply of the clock for processing in a period in which the clock for processing is not required. An ASIC itself realizes a low power consumption function (a clock stop function) without requiring control from a CPU or the like as in the conventional sleep function. Thus, it is possible to effectively reduce power consumption of the ASIC compared with that in the past.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: August 10, 2010
    Assignees: Toshiba Tec Kabushiki Kaisha, Kabushiki Kaisha Toshiba
    Inventor: Junji Yamada
  • Publication number: 20100177348
    Abstract: The present invention provides a page image managing technique that enables editing of N-in-1-arranged page images. A page image managing apparatus includes: a number-of-pages-information acquiring unit configured to acquire number-of-input-pages information indicating the number of arrayed pages of plural page images arrayed in a reading target original document; an image processing unit configured to slice, on the basis of the number-of-input-pages information acquired by the number-of-pages-information acquiring unit, the plural page images from a read image of the original document and apply image processing corresponding to the number-of-input-pages information acquired by the number-of-pages-information acquiring unit to the respective sliced page images; and a storage control unit configured to cause a predetermined storage area to store the respective plural page images processed by the image processing unit as separate page images.
    Type: Application
    Filed: January 13, 2010
    Publication date: July 15, 2010
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA TEC KABUSHIKI KAISHA
    Inventor: Junji Yamada
  • Publication number: 20100096758
    Abstract: An electric power semiconductor device including first and second circuit patterns formed on main surfaces of first and second insulating substrates, respectively, first and second semiconductor chips mounted on the first and second circuit patterns, respectively, a multilayer electrode plate assembly disposed between the first and second insulating substrates, having first, second and third electrode terminals provided with a distance from each other, a first connecting conductor made by wire bonding for connecting the first and second semiconductor chips to the first and second electrode terminals, and a second connecting conductor having an extending portion extended from a part of the third electrode terminal to be connected to the second circuit pattern, and the connection between the extending portion of the third electrode terminal and the second circuit pattern is implemented by a solder.
    Type: Application
    Filed: December 24, 2009
    Publication date: April 22, 2010
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Junji YAMADA, Seiji Saiki
  • Patent number: 7663252
    Abstract: An electric power semiconductor device including first and second circuit patterns formed on main surfaces of first and second insulating substrates, respectively, first and second semiconductor chips mounted on the first and second circuit patterns, respectively, a multilayer electrode plate assembly disposed between the first and second insulating substrates, having first, second and third electrode terminals provided with a distance from each other, a first connecting conductor made by wire bonding for connecting the first and second semiconductor chips to the first and second electrode terminals, and a second connecting conductor having an extending portion extended from a part of the third electrode terminal to be connected to the second circuit pattern, and the connection between the extending portion of the third electrode terminal and the second circuit pattern is implemented by a solder.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: February 16, 2010
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Junji Yamada, Seiji Saiki