Patents by Inventor Junji Yamada

Junji Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7084463
    Abstract: A semiconductor device includes: a gate electrode on a semiconductor substrate through a gate insulated film; source/drain regions to be adjacent to said gate electrode; and an Al wiring through an interlayer insulating film covering said gate electrode, wherein impurity ions are implanted into a surface of said semiconductor substrate using as a mask said Al wiring, and a protection film is formed on the Al wiring so that the Al wiring is not exposed when said interlayer insulating film is etched.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: August 1, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Junji Yamada, Yutaka Yamada, Junichi Ariyoshi
  • Patent number: 6984883
    Abstract: An insulating substrate (17) includes a surface conductive layer (25) fixedly laminated on a surface of the plate-like semiconductor body (21) via a surface side fixing member (24, 26). The surface side fixing member (24, 26) includes a first fixing portion (26) for fixing one part (25a) of the surface conductive layer (25) located underneath the joint portion (15) of the electrode terminal (14), and a second fixing portion (24) for fixing the other part (25b) of the surface conductive layer (25) which is not located underneath the joint portion (15), and a fixing strength exhibited by the first fixing portion (26) is smaller than that exhibited by the second fixing portion (24).
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: January 10, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Junji Yamada, Seiji Saiki
  • Publication number: 20050236617
    Abstract: One of aspects of the present invention is to provide a semiconductor device, which includes an insulating substrate, and a semiconductor chip mounted on the insulating substrate. The semiconductor chip has a chip electrode thereon. The semiconductor device also includes a first terminal electrically connected with the chip electrode through a first metal wire, and a second terminal electrically connected with the chip electrode through a second metal wire that is more likely to be disconnected than the first metal wire. A signal of disconnection of the second metal wire is output at the second terminal.
    Type: Application
    Filed: November 12, 2004
    Publication date: October 27, 2005
    Inventor: Junji Yamada
  • Publication number: 20050162399
    Abstract: A displaying and inputting apparatus includes a touch panel display, a layout information memory which stores a plurality of layout information which sets a layout of a plurality of functions displayed on the touch panel display, a selector which selects one layout information from the plurality of layout information, and a control unit which displays a function on a touch panel display based on the layout information selected by the selector.
    Type: Application
    Filed: January 23, 2004
    Publication date: July 28, 2005
    Inventor: Junji Yamada
  • Patent number: 6809410
    Abstract: A power semiconductor module with a connection structure in which an electrode terminal whose one end is connected with an electric power semiconductor device which is resin sealed inside of the case, is exposed along an outer surface of a case for taking out electrode from the semiconductor device, and is electrically connected to an electrode for external connection disposed on the electrode terminal, wherein a female screw hole for screwing is provided on side of the outer surface of the case, a male screw member formed at its opposite ends with screw threads is threadedly engaged with the female screw hole through the electrode terminal.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: October 26, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Junji Yamada
  • Publication number: 20040135256
    Abstract: A nonvolatile semiconductor memory device includes a plurality of memory transistors, a plurality of insulating layers disposed over the transistors, and a plurality of metal layers. Each of the metal layers is disposed on one of the insulating layers. The device also includes a plurality of metal plugs disposed over corresponding memory transistors. Each of the metal plugs filling in a contact hole formed in one of the insulating layers and electrically connecting the metal layers disposed on a top side and a bottom side of the corresponding insulating layer. A top metal layer of the plurality of metal layers is configured to provide bit lines that correspond to the memory transistors, the metal plugs are vertically aligned, and one of the insulating layers is configured so that whether one of the memory transistors is connected to a corresponding bit line is determined by whether a metal plug corresponding to the memory transistor exists in the insulating layer.
    Type: Application
    Filed: October 30, 2003
    Publication date: July 15, 2004
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Shuichi Takahashi, Fumiko Shikakura, Shinya Mori, Junji Yamada, Yutaka Yamada, Toshimitsu Taniguchi
  • Publication number: 20040113258
    Abstract: An insulating substrate (17) includes a surface conductive layer (25) fixedly laminated on a surface of the plate-like semiconductor body (21) via a surface side fixing member (24, 26). The surface side fixing member (24, 26) includes a first fixing portion (26) for fixing one part (25a) of the surface conductive layer (25) located underneath the joint portion (15) of the electrode terminal (14), and a second fixing portion (24) for fixing the other part (25b) of the surface conductive layer (25) which is not located underneath the joint portion (15), and a fixing strength exhibited by the first fixing portion (26) is smaller than that exhibited by the second fixing portion (24).
    Type: Application
    Filed: September 29, 2003
    Publication date: June 17, 2004
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Junji Yamada, Seiji Saiki
  • Publication number: 20040085554
    Abstract: One processing section 131 executes a process of generating image data K representing a black image on the basis of the image data Y, M, and C, and sequentially executes a process of removing elements of the black image contained in the image data Y, from the image data Y, a process of removing the elements of the black image contained in the image data M, from the image data M, and a process of removing the elements of the black image contained in the image data C, from the image data C.
    Type: Application
    Filed: November 1, 2002
    Publication date: May 6, 2004
    Applicant: TOSHIBA TEC KABUSHIKI KAISHA
    Inventor: Junji Yamada
  • Publication number: 20040041253
    Abstract: Semiconductor chips are connected to electrode terminals (6a, 6b) by wire bonding, and connecting conductors connect extending portions (60b, 60c) extending from a part of the electrode terminals (6b, 6c) to the circuit patterns (3a, 3b) by soldering, and thus the wire bonding points of the electrode terminals are reduced to thereby reduce an electric resistance and suppress heat generation and voltage drop.
    Type: Application
    Filed: August 27, 2003
    Publication date: March 4, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Junji Yamada, Seiji Saiki
  • Patent number: 6576518
    Abstract: Disclosed is a method of manufacturing a semiconductor device including a gate electrode on a semiconductor substrate through a gate insulated film; source/drain regions formed to be adjacent to the gate electrode; and an Al wiring formed through an interlayer insulating film covering the gate electrode, wherein impurity ions are implanted in a surface layer of the substrate using the Al wiring and a photoresist formed thereon as a mask, and wherein no photoresist is formed on the Al wiring arranged above regions in which the impurity ions are implanted in adjacent elements.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: June 10, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Junji Yamada, Yutaka Yamada, Junichi Ariyoshi
  • Patent number: 6495604
    Abstract: The present invention provides a compound represented by the formula: wherein R represents an aliphatic hydrocarbon group optionally having substituents, an aromatic hydrocarbon group optionally having substituents, a heterocyclic group optionally having substituents, a group represented by the formula: OR1 (wherein R1 represents a hydrogen atom or an aliphatic hydrocarbon group optionally having substituents) or a group represented by the formula: wherein R1b represents a hydrogen atom or an aliphatic hydrocarbon group optionally having substituents, R1c is, same with or different from R1b, a hydrogen atom or an aliphatic hydrocarbon group optionally having substituents, R0 represents a hydrogen atom or an aliphatic hydrocarbon group, or R and R0 represents a bond with each other, Ar represents an aromatic hydrocarbon group optionally having substituents, and n is an integer of 1 to 4, or a salt thereof, which is a agent for preventing or treating disease
    Type: Grant
    Filed: August 14, 2000
    Date of Patent: December 17, 2002
    Assignee: Takeda Chemical Industries, Ltd.
    Inventors: Yuzo Ichimori, Masayuki Ii, Katsumi Itoh, Tomoyuki Kitazaki, Junji Yamada
  • Publication number: 20020173103
    Abstract: The method of manufacturing a semiconductor device comprises the steps of: forming a gate electrode on a semiconductor substrate through a gate insulated film; forming source/drain regions to be adjacent to the gate electrode forming an Al wiring through an interlayer insulating film covering the gate electrode; and implanting impurity ions into a surface of the semiconductor substrate using as a mask the Al wiring and a photoresist formed thereon, thereby writing information into each of elements constituting a mask ROM and changing an outputting manner at an output port.
    Type: Application
    Filed: March 13, 2002
    Publication date: November 21, 2002
    Inventors: Junji Yamada, Yutaka Yamada, Junichi Ariyoshi
  • Publication number: 20020140078
    Abstract: To provide a power semiconductor device to which a large current can be applied and which can be fabricated compactly in a shorter time. A power semiconductor device with an electrode structure for taking out electrodes from a power semiconductor element mounted on one of a plurality of circuit patterns formed on an insulating substrate inside of a case up to an external-connection terminal exposed outside of the case is used in which the external-connection terminal is insert-formed on the body of the case, exposed to the outside of the case at one end of the terminal while the terminal is joined at its other end to a circuit pattern different from a circuit pattern on which the power semiconductor element is mounted, and connected with the power semiconductor element through a wire member bonded to the face opposite to the junction face of the terminal.
    Type: Application
    Filed: September 18, 2001
    Publication date: October 3, 2002
    Inventor: Junji Yamada
  • Publication number: 20020130423
    Abstract: A semiconductor device includes: a gate electrode on a semiconductor substrate through a gate insulated film; source/drain regions to be adjacent to said gate electrode; and an Al wiring through an interlayer insulating film covering said gate electrode, wherein impurity ions are implanted into a surface of said semiconductor substrate using as a mask said Al wiring, and a protection film is formed on the Al wiring so that the Al wiring is not exposed when said interlayer insulating film is etched.
    Type: Application
    Filed: March 11, 2002
    Publication date: September 19, 2002
    Inventors: Junji Yamada, Yutaka Yamada, Junichi Ariyoshi
  • Publication number: 20020062973
    Abstract: A power semiconductor module with a connection structure in which an electrode terminal whose one end is connected with an electric power semiconductor device which is resin sealed inside of the case, is exposed along an outer surface of a case for taking out electrode from the semiconductor device, and is electrically connected to an electrode for external connection disposed on the electrode terminal, wherein a female screw hole for screwing is provided on side of the outer surface of the case, a male screw member formed at its opposite ends with screw threads is threadedly engaged with the female screw hole through the electrode terminal.
    Type: Application
    Filed: April 10, 2001
    Publication date: May 30, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Junji Yamada
  • Patent number: 6265582
    Abstract: The present invention relates to a method for producing a compound of the formula: wherein R1 is an optionally substituted hydrocarbon group; R2 is H or an optionally substituted hydrocarbon group; and Q is an optionally substituted heterocyclic group, or a salt thereof which comprises subjecting a compound of the formula: wherein R1 has the same meaning as defined above, or a salt thereof to a nitration reaction (a), and further subjecting the resulting mixture without isolating/purifying the resulting compound of the formula: wherein R1 has the same meaning as defined above, or a salt thereof to a reaction (b) with a compound of the formula: Q—CH2—NH—R2  [III] wherein each symbol has the same meaning as defined above, or a salt thereof.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: July 24, 2001
    Assignee: Takeda Chemical Industries, Ltd.
    Inventors: Hideki Uneme, Yasuo Kamiya, Masato Konobe, Junji Yamada
  • Patent number: 6047891
    Abstract: A magnetic head 17 reads first character information having a predetermined presentation form magnetically recorded on a photographic film 2, and an exposing unit 5 exposes a photosensitive material 3 with a photographic image of the photographic film. A character-information processing unit 70 converts the first character information read by the magnetic head 17 into second character information having a different presentation form than the first character information in accordance with an instructed conversion rule, and a character exposing unit 30 prints the second character information on the photosensitive material 3 in correlation with the photographic image of the photographic film 2.
    Type: Grant
    Filed: August 23, 1996
    Date of Patent: April 11, 2000
    Assignee: Noritsu Koki Co., Ltd.
    Inventor: Junji Yamada
  • Patent number: 5979820
    Abstract: A film magazine includes a take-up mechanism for a take-up mechanism for taking up a film in the form of roll, with the film being releasable therefrom. The magazine further includes a support mechanism for supporting the film roll formed by the take-up mechanism in such a manner as to allow a rotational axis of the formed roll to be adjustable in position in accordance with variation in the outer diameter of the roll resulting from the take-up or unwinding operation of the film.
    Type: Grant
    Filed: July 24, 1998
    Date of Patent: November 9, 1999
    Assignee: Noritsu Koki Co., Ltd.
    Inventors: Junji Yamada, Hiroshi Miyawaki, Toru Yoshikawa, Junichi Yamamoto
  • Patent number: 5933566
    Abstract: A film analyzer for displaying print images simulated from picture frames of a photographic film on a video display. The analyzer includes a film reader for picking up image data of the picture frames, a first memory for storing the picked-up image data, an exposure condition calculating unit for calculating an exposure condition for each of the picture frames based on the image data, a simulating unit for simulating the image data read from the first memory means into a print image which is expected to be obtained as a print by exposing each picture frame under the exposure condition, a second memory for storing the simulated print image and a display control unit for causing the print image stored at the second memory to be displayed on the video display.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: August 3, 1999
    Assignee: Noritsu Koki Co., Ltd.
    Inventors: Takuji Kishi, Junji Yamada
  • Patent number: D476959
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: July 8, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Junji Yamada, Seiji Saiki