Abstract: A proton therapy system based on a compact superconducting cyclotron, including: a superconducting cyclotron system, an energy selection system, a beam transport system, a fixed therapy room subsystem and a rotating frame therapy subsystem; a fixed-energy proton beam extracted from a superconducting cyclotron of the superconducting cyclotron system is adjusted into a continuous and adjustable proton beam of 70 MeV to 200 MeV by the energy selection system, thus realizing a longitudinal adjustment for a proton range during treating a tumor, and the continuous and adjustable proton beam is respectively transmitted to the fixed therapy room subsystem and the rotating frame therapy subsystem by the beam transport system. The cooperative control of the superconducting cyclotron system, the energy selection system, the beam transport system and the therapy head realizes the transverse expansion of proton beams, thus realizing intensity modulated radiation therapy for the tumor.

Abstract: A method for conversion attribution. The method includes obtaining a first identifier associated with a first device, obtaining a second identifier associated with a second device, bridging the first identifier and the second identifier based on a determination, made by a probabilistic classifier, that the first identifier and the second identifier are associated with a common user, and attributing, using the bridge, a conversion on a website accessed using the second device.

Abstract: The invention discloses a method for adjusting particle orbit alignment by using a first harmonic in a cyclotron, including the following steps: generating a correcting magnetic field through eight coils symmetrically about the middle plane; arranging the positions of the coils and the currents applied, so that they can generate a first harmonic of which the amplitude and phase are arbitrarily adjustable; according to the actual eccentricity of the particle orbit, adjusting the magnitude and direction of the currents applied to the coils, and optimizing the alignment of the particle trajectory. By controlling an external DC power source of the accelerator and combining the real-time feedback of the beam detection of the accelerator, the invention may perform real-time adjustment during the debugging and operation of the accelerator, with high feasibility and operability; compared with traditional methods, the invention may achieve real-time adjustment during the debugging and operation of the accelerator.

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract: The invention discloses a method for adjusting particle orbit alignment by using a first harmonic in a cyclotron, including the following steps: generating a correcting magnetic field through eight coils symmetrically about the middle plane; arranging the positions of the coils and the currents applied, so that they can generate a first harmonic of which the amplitude and phase are arbitrarily adjustable; according to the actual eccentricity of the particle orbit, adjusting the magnitude and direction of the currents applied to the coils, and optimizing the alignment of the particle trajectory. By controlling an external DC power source of the accelerator and combining the real-time feedback of the beam detection of the accelerator, the invention may perform real-time adjustment during the debugging and operation of the accelerator, with high feasibility and operability; compared with traditional methods, the invention may achieve real-time adjustment during the debugging and operation of the accelerator.

Abstract: Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material. The method further includes forming an epitaxial material with doped regions on the mesa structure and forming gate material over at least the plurality of fin structures. The method further includes planarizing at least the gate material such that the gate material and the epitaxial material are of a same height. The method further includes forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material.

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract: Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material. The method further includes forming an epitaxial material with doped regions on the mesa structure and forming gate material over at least the plurality of fin structures. The method further includes planarizing at least the gate material such that the gate material and the epitaxial material are of a same height. The method further includes forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material.

Abstract: An electrostatic discharge protection circuit includes a power clamp device, a timing circuit including a first resistor, a first capacitor that is connected with the first resistor at a first node, and a second capacitor that is connected to a second node, a logic gate including a first input connected with the first node, a second input connected with the second node, and an output connected with the power clamp device, and a decoder device connected with a first address pin and a second address pin. The first address pin and the second address pin are used to detect the power clamp device switching on at time of power on and draining current.

Abstract: A preparation method for silver nanowires, including: dissolving a dispersant in a tribasic alcohol to get a viscous clear solution, dissolving the silver nitrate in a tribasic alcohol to get a clear solution; then, adding the silver nitrate solution to the dispersant solution for uniform mixing, finally, transferring the mixed solution into a reaction kettle, putting into an oven with a set temperature (170˜200° C.), and ending the reaction after a period of time. The mother solution of silver nanowires is diluted with alcohol and then centrifuged to separate organics, the novel silver nanowires with a uniform aspect ratio and nodes are obtained.

Abstract: An electrostatic discharge protection circuit includes a transistor device, a first timing circuit including a first resistor and a first capacitor that is connected with the first resistor at a first node, a second timing circuit including a second resistor and a second capacitor that is connected with the second resistor at a second node, and a logic gate including a first input connected with the first node, a second input coupled with the second node, and an output connected with the transistor device.

Abstract: An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.

Abstract: Silicon controlled rectifiers (SCR), methods of manufacture and design structures are disclosed herein. The method includes forming a common P-well on a buried insulator layer of a silicon on insulator (SOI) wafer. The method further includes forming a plurality of silicon controlled rectifiers (SCR) in the P-well such that N+ diffusion cathodes of each of the plurality of SCRs are coupled together by the common P-well.

Abstract: Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material. The method further includes forming an epitaxial material with doped regions on the mesa structure and forming gate material over at least the plurality of fin structures. The method further includes planarizing at least the gate material such that the gate material and the epitaxial material are of a same height. The method further includes forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material.

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an cathode on a substrate and a anode on the substrate. The anode is in electrical contact with the cathode. The method further includes forming a device between the cathode and the anode. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract: An apparatus includes a device, a comparison circuit, and a switch. The device includes a first terminal coupled to a first power supply signal, and a second terminal coupled to a ground reference. The comparison circuit is configured to compare a first voltage level on the first power supply signal to a second voltage level of a second power supply signal, and enable the device in response to a determination that the first voltage level is greater than the second voltage level. The switch circuit is configured to couple a power supply terminal of the comparison circuit to the first power supply signal in response to determining that the first voltage level is greater than the second voltage level, and to couple the power supply terminal to the second power supply signal in response to determining that the first voltage level is less than the second voltage level.

Abstract: Provided is a method for producing a tissue-like construct having cultured cells organized in an aligned manner, especially, a cardiac tissue-like construct. The tissue-like construct prepared by this method is also provided. Further provided are a device for evaluating cellular electrophysiological functions and a method for evaluating cellular electrophysiological functions. Furthermore, a sheet-like cell culture scaffold is also provided.

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract: Aspects of the disclosure provide a multi-gate field effect transistor (FET) formed on a bulk substrate that includes an isolated fin and methods of forming the same. In one embodiment, the multi-gate FET includes: a plurality of silicon fin structures formed on the bulk substrate, each silicon fin structure including a body region, a source region, and a drain region; wherein a bottom portion the body region of each silicon fin structure includes a tipped shape to isolate the body region from the bulk substrate, and wherein the plurality of silicon fin structures are attached to the bulk substrate via at least a portion of the source region, or at least a portion of the drain region, or both.

Abstract: An electrostatic discharge protection circuit includes a transistor device, a first timing circuit including a first resistor and a first capacitor that is connected with the first resistor at a first node, a second timing circuit including a second resistor and a second capacitor that is connected with the second resistor at a second node, and a logic gate including a first input connected with the first node, a second input coupled with the second node, and an output connected with the transistor device.