Abstract: Device structures, design structures, and fabrication methods for a metal-oxide-semiconductor field-effect transistor. A gate structure is formed on a top surface of a substrate. First and second trenches are formed in the substrate adjacent to a sidewall of the gate structure. The second trench is formed laterally between the first trench and the first sidewall. First and second epitaxial layers are respectively formed in the first and second trenches. A contact is formed to the first epitaxial layer, which serves as a drain. The second epitaxial layer in the second trench is not contacted so that the second epitaxial layer serves as a ballasting resistor.

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract: Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material. The method further includes forming an epitaxial material with doped regions on the mesa structure and forming gate material over at least the plurality of fin structures. The method further includes planarizing at least the gate material such that the gate material and the epitaxial material are of a same height. The method further includes forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material.

Abstract: Diodes and resistors for integrated circuits are provided. Deep trenches (DTs) are integrated into the diodes and resistors for the purposes of thermal conduction. The deep trenches facilitate conduction of heat from a semiconductor-on-insulator substrate to a bulk substrate. Semiconductor fins may be formed to align with the deep trenches.

Abstract: In an embodiment, an ESD protection circuit is provided in which diodes may be formed between N+ and P+ diffusions within an insulated semiconductor region and in which additional diodes may be formed between adjacent insulated regions of opposite conduction type as well. The diodes may be used in parallel to form an ESD protection circuit, which may have low on resistance and may sink high ESD current per unit area. To support the formation of the ESD protection circuit, each silicon region may have alternating N+ and P+ diffusions, and adjacent silicon regions may have N+ and P+ diffusions alternating in opposite locations. That is a perpendicular drawn between the N+ diffusions of one adjacent region may intersect P+ diffusions in the other adjacent region, and vice versa.

Abstract: An electrostatic discharge protection circuit is disclosed. A method of manufacturing a semiconductor structure includes forming a semiconductor controlled rectifier including a first plurality of fingers between an n-well body contact and an anode in an n-well, and a second plurality of fingers between a p-well body contact and a cathode in a p-well.

Abstract: Device structures and design structures for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.

Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

Abstract: An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.

Abstract: An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.

Abstract: Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material. The method further includes forming an epitaxial material with doped regions on the mesa structure and forming gate material over at least the plurality of fin structures. The method further includes planarizing at least the gate material such that the gate material and the epitaxial material are of a same height. The method further includes forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material.

Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

Abstract: Circuits and methods of fabricating circuits that provide electrostatic discharge protection, as well as methods of protecting an integrated circuit from electrostatic discharge. The protection circuit may include a power clamp device, a timing circuit including a resistor and a capacitor that is coupled with the resistor at a node, and a power clamp device coupled with the timing circuit at the node. The capacitor includes a plurality of capacitor elements. The protection circuit further includes a plurality of electronic fuses. Each electronic fuse is coupled with a respective one of the capacitor elements. A field effect transistor may be coupled in parallel with the resistor of the timing circuit, and may be used to bypass the resistor to provide a programming current to any electronic fuse coupled with a capacitor element of abnormally low impedance.

Abstract: Circuits and methods for providing electrostatic discharge protection. The protection circuit may include a power clamp device, a timing circuit including a resistor and a capacitor that is coupled with the resistor at a node, a transmission gate configured to selectively connect the node of the timing circuit with the power clamp device, and a control circuit coupled with the node. The control circuit is configured to control the transmission gate based upon whether or not the capacitor is defective. The timing circuit may be deactivated if the capacitor in the timing circuit is defective and the associated chip is powered. Alternatively, the timing circuit may be activated if the capacitor in the timing circuit is not defective.

Abstract: An electronic fuse link with lower programming current for high performance and self-aligned methods of forming the same. The invention provides a horizontal e-fuse structure in the middle of the line. A reduced fuse link width is achieved by spacers on sides of pair of dummy or active gates, to create sub-lithographic dimension between gates with spacers to confine a fuse link. A reduced height in the third dimension on the fuse link achieved by etching the link, thereby creating a fuse link having a sub-lithographic size in all dimensions. The fuse link is formed over an isolation region to enhanced heating and aid fuse blow.

Abstract: Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.

Abstract: A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes.

Abstract: Methods and systems for altering the electrical resistance of a wiring path. The electrical resistance of the wiring path is compared with a target electrical resistance value. If the electrical resistance of the wiring path exceeds the target electrical resistance value, an electrical current is selectively applied to the wiring path to physically alter a portion of the wiring path. The current may be selected to alter the wiring path such that the electrical resistance drops to a value less than or equal to the target electrical resistance value.

Abstract: Various embodiments include dual three-dimensional (3D) resistor structures and methods of forming such structures. In some embodiments, a dual 3D resistor structure includes: a dielectric layer having a first set of trenches extending in a first direction through the dielectric layer; and a second set of trenches overlayed on the first set of trenches, the second set of trenches extending in a second direction through the dielectric layer, the second set of trenches and the first set of trenches forming at least one dual 3D trench; and a resistor material overlying the dielectric layer and at least partially filling the at least one dual 3D trench along the first direction and the second direction.