Abstract: The present disclosure proposes an improved method of potting a vent of a secondary battery cell, and according to aspects of the present disclosure, there is provided a secondary battery module including a battery cell including terminals and a vent, and a vent potting plate including a base plate configured to cover at least the vent of the battery cell and a potting material accommodation portion provided on the base plate and located at a position corresponding to a position of the vent of the battery cell.

Abstract: A semiconductor device may include a substrate including an active pattern, a channel pattern on the active pattern, a source/drain pattern, a gate electrode, and an insulation pattern. The channel pattern may include semiconductor patterns that are spaced apart from each other and vertically stacked. A lowermost one of the semiconductor patterns may be a first semiconductor pattern. The source/drain pattern may be connected to the semiconductor patterns. The gate electrode may be on the semiconductor patterns and may include a plurality of inner electrodes below the semiconductor patterns except the first semiconductor pattern. The insulation pattern may be between the first semiconductor pattern and the active pattern. The insulation pattern may include a dielectric pattern and a protection layer. The protection layer may be between the dielectric pattern and the first semiconductor pattern. The protection layer may be between the dielectric pattern and the active pattern.

Abstract: A compound for an organic optoelectronic device, a composition for an organic optoelectronic device including the same, an organic optoelectronic device, and a display device, the compound being represented by Chemical Formula 1:

Abstract: Provided is a semiconductor device which includes: a 1st channel structure; a 2nd channel structure vertically above the 1st channel structure; and a middle isolation structure including a plurality of middle isolation layers between the 1st channel structure and the 2nd channel structure, wherein the plurality of middle isolation layers are separated in a vertical direction.

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a substrate; an insulator on an upper surface of the substrate; a transistor between the substrate and the insulator, the transistor comprising: channel layers that are spaced apart from each other in a first direction that is perpendicular to the upper surface of the substrate; and a gate structure on the channel layers and the insulator, wherein a width of the insulator in a second direction that is parallel with the upper surface of the substrate is equal or substantially equal to a width of an uppermost one of the channel layers in the second direction.

Abstract: Provided is a semiconductor device which may include: a plurality of 1st channel layers; a 1st source/drain region on the plurality of 1st channel layers; and a gate structure including a 1st work-function metal layer on the plurality of 1st channel layers, wherein the 1st work-function metal layer includes a 1st layer between the plurality of 1st channel layers and a 2nd layer on side surfaces of the plurality of 1st channel layers, and atomic percent of a 1st metal in the 1st layer is different from atomic percent of the 1st metal in the 2nd layer.

Abstract: A semiconductor memory device includes: a substrate having first and second channel structures extending in a first direction arranged spaced apart in a second direction; a first gate structure disposed on the first channel structure; a second gate structure disposed on the second channel structure; first source/drain regions disposed on opposite sides of the first gate structure; second source/drain regions disposed on opposite sides of the second gate structure; a gate separation pattern disposed between the gate structures to directly contact the gate structures and having an upper surface disposed at a level lower than an upper surface of the gate structures along a third direction; and a gate capping layer disposed on the gate structures and having an extension portion disposed between the gate structures such that the extension portion directly contacts the gate structures, the gate capping layer being connected to the gate separation pattern.

Abstract: A semiconductor device may include a substrate including first and second active regions, which are adjacent to each other, first and second active patterns provided on the first and second active regions, respectively, and a gate electrode extended to cross the first and second active patterns. The gate electrode may include first and second electrode portions provided on the first and second active regions, respectively. The second electrode portion may include a first metal pattern, an etch barrier pattern, a second metal pattern, and a third metal pattern sequentially covering the second active pattern. The first electrode portion may include a second metal pattern covering the first active pattern. The etch barrier pattern may be in contact with the first metal pattern and the second metal pattern, and the etch barrier pattern may be thinner than the first metal pattern and thinner than the second metal pattern.

Abstract: A semiconductor device includes a substrate, a lower channel stack on the substrate, an upper channel stack on the lower channel stack, a gate electrode extending around the lower channel stack and the upper channel stack, a gate cut region that is on the substrate and includes an insulating material, a semiconductor material layer between the upper channel stack and the gate cut region, and an insulating layer that is between the semiconductor material layer and the upper channel stack.

Abstract: A semiconductor device may include a substrate including first and second active regions, which are adjacent to each other, first and second active patterns provided on the first and second active regions, respectively, and a gate electrode extended to cross the first and second active patterns. The gate electrode may include first and second electrode portions provided on the first and second active regions, respectively. The second electrode portion may include a first metal pattern, an etch barrier pattern, a second metal pattern, and a third metal pattern sequentially covering the second active pattern. The first electrode portion may include a second metal pattern covering the first active pattern. The etch barrier pattern may be in contact with the first metal pattern and the second metal pattern, and the etch barrier pattern may be thinner than the first metal pattern and thinner than the second metal pattern.