Abstract: A semiconductor device may include a first pattern and a second pattern extending in a first direction, a second semiconductor pattern on the first semiconductor pattern, a source/drain pattern connected to the first and second semiconductor patterns, a gate electrode extending in a second direction on the first semiconductor pattern and the second semiconductor pattern, the gate electrode including an inner electrode between the first semiconductor pattern and the second semiconductor pattern, a gate dielectric layer between the gate electrode and the first semiconductor pattern and between the gate electrode and the second semiconductor pattern, and an insulation pattern between the first semiconductor pattern and the first pattern, wherein the insulation pattern may include a dielectric pattern and a protection layer, the protection layer may be between the dielectric pattern and the first semiconductor pattern, and the protection layer may be between the dielectric pattern and the first pattern.

Abstract: An electronic apparatus, including a processor connected with a microphone, a memory and a communication interface, and configured to: based on receiving a user voice through the microphone, acquire an operation result by inputting the user voice into the first neural network model, and identify at least one device corresponding to the user voice by inputting the operation result into the second neural network model, and control the communication interface to transmit the operation result to the at least one device, wherein the first neural network model is configured to, after only some layers of a third neural network model trained to identify a text from a voice are additionally trained, include only the additionally trained some layers, and wherein the second neural network model is trained to identify a device corresponding to a voice.

Abstract: Provided is a method of inferring an interest associated with a user, the method including obtaining time span information for determining interest associated with the user from a query; obtaining user interaction-based semantic index information from at least one system log knowledge graph, the at least one system log knowledge graph corresponding to the time span information; searching for at least one contact node, based on user interaction-based semantic index information, in at least one user log knowledge graph, the at least one user log knowledge graph corresponding to the time span information, each of user log knowledge graph including, as respective nodes, entities related to activity information associated with the user; and obtaining the interest associated with the user corresponding to the time span information, based on at least one node that satisfies a preset condition, from a user log knowledge graph including the at least one contact node.

Abstract: A semiconductor memory device includes: a substrate having a first channel structure and a second channel structure respectively extending in a first direction and arranged in a second direction perpendicular to the first direction; a first gate structure disposed on the first channel structure and extending in the second direction on the substrate; a second gate structure disposed on the second channel structure and extending in the second direction; first source/drain regions respectively disposed on opposite sides of the first gate structure; second source/drain regions respectively disposed on opposite sides of the second gate structure; a gate separation pattern disposed between the first and second gate structures and having an upper surface at a level lower than that of an upper surface of each of the first and second gate structures, including a first insulating material; and a gate capping layer disposed on the first and second gate structures.

Abstract: An electronic apparatus and a control method thereof are provided. The electronic apparatus includes a communication interface configured to receive content comprising image data and speech data; a memory configured to store a language contextual model trained with relevance between words; a display; and a processor configured to: extract an object and a character included in the image data, identify an object name of the object and the character, generate a bias keyword list comprising an image-related word that is associated with the image data, based on the identified object name and the identified character, convert the speech data to a text based on the bias keyword list and the language contextual model, and control the display to display the text that is converted from the speech data, as a caption.

Abstract: A shader engine device for performing shading includes an instruction buffer configured to store instructions, a controller configured to schedule execution of the per-wave instructions, an arithmetic logic unit (ALU) configured to perform a graphics operation, and a general-purpose register configured to store an intermediate value of the graphics operation. The controller is further configured to change a precision mode of the instructions to a high precision mode, based on heuristic precision modulated shading (PMS), the instructions being associated with a source operand of a branch.

Abstract: A graphics processing unit (GPU) includes a GPU memory including a first memory and a second memory and a plurality of shader arrays each including a plurality of shader modules. Each of the shader modules includes a data address generation circuit configured to update a search pattern for at least one piece of input data by using pipeline information stored in the first memory and, based on the search pattern that has been updated, generate at least one memory address corresponding to the input data, a data loading circuit configured to load the input data from the second memory based on the memory address and the pipeline information, a controller configured to schedule at least one instruction for performing a graphics pipeline, and a processing circuit configured to perform shading on the input data.

Abstract: Provided is a semiconductor device which includes: a channel structure; a source/drain region on the channel structure; a gate structure on the channel structure; and a bottom isolation layer below the gate structure and the source/drain region, wherein the bottom isolation layer is thicker vertically below the gate structure than vertically below the source/drain region.

Abstract: The present disclosure proposes an improved method of potting a vent of a secondary battery cell, and according to aspects of the present disclosure, there is provided a secondary battery module including a battery cell including terminals and a vent, and a vent potting plate including a base plate configured to cover at least the vent of the battery cell and a potting material accommodation portion provided on the base plate and located at a position corresponding to a position of the vent of the battery cell.

Abstract: A semiconductor device may include a substrate including an active pattern, a channel pattern on the active pattern, a source/drain pattern, a gate electrode, and an insulation pattern. The channel pattern may include semiconductor patterns that are spaced apart from each other and vertically stacked. A lowermost one of the semiconductor patterns may be a first semiconductor pattern. The source/drain pattern may be connected to the semiconductor patterns. The gate electrode may be on the semiconductor patterns and may include a plurality of inner electrodes below the semiconductor patterns except the first semiconductor pattern. The insulation pattern may be between the first semiconductor pattern and the active pattern. The insulation pattern may include a dielectric pattern and a protection layer. The protection layer may be between the dielectric pattern and the first semiconductor pattern. The protection layer may be between the dielectric pattern and the active pattern.

Abstract: A compound for an organic optoelectronic device, a composition for an organic optoelectronic device including the same, an organic optoelectronic device, and a display device, the compound being represented by Chemical Formula 1:

Abstract: Provided is a semiconductor device which includes: a 1st channel structure; a 2nd channel structure vertically above the 1st channel structure; and a middle isolation structure including a plurality of middle isolation layers between the 1st channel structure and the 2nd channel structure, wherein the plurality of middle isolation layers are separated in a vertical direction.

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a substrate; an insulator on an upper surface of the substrate; a transistor between the substrate and the insulator, the transistor comprising: channel layers that are spaced apart from each other in a first direction that is perpendicular to the upper surface of the substrate; and a gate structure on the channel layers and the insulator, wherein a width of the insulator in a second direction that is parallel with the upper surface of the substrate is equal or substantially equal to a width of an uppermost one of the channel layers in the second direction.

Abstract: Provided is a semiconductor device which may include: a plurality of 1st channel layers; a 1st source/drain region on the plurality of 1st channel layers; and a gate structure including a 1st work-function metal layer on the plurality of 1st channel layers, wherein the 1st work-function metal layer includes a 1st layer between the plurality of 1st channel layers and a 2nd layer on side surfaces of the plurality of 1st channel layers, and atomic percent of a 1st metal in the 1st layer is different from atomic percent of the 1st metal in the 2nd layer.

Abstract: A semiconductor memory device includes: a substrate having first and second channel structures extending in a first direction arranged spaced apart in a second direction; a first gate structure disposed on the first channel structure; a second gate structure disposed on the second channel structure; first source/drain regions disposed on opposite sides of the first gate structure; second source/drain regions disposed on opposite sides of the second gate structure; a gate separation pattern disposed between the gate structures to directly contact the gate structures and having an upper surface disposed at a level lower than an upper surface of the gate structures along a third direction; and a gate capping layer disposed on the gate structures and having an extension portion disposed between the gate structures such that the extension portion directly contacts the gate structures, the gate capping layer being connected to the gate separation pattern.

Abstract: A semiconductor device may include a substrate including first and second active regions, which are adjacent to each other, first and second active patterns provided on the first and second active regions, respectively, and a gate electrode extended to cross the first and second active patterns. The gate electrode may include first and second electrode portions provided on the first and second active regions, respectively. The second electrode portion may include a first metal pattern, an etch barrier pattern, a second metal pattern, and a third metal pattern sequentially covering the second active pattern. The first electrode portion may include a second metal pattern covering the first active pattern. The etch barrier pattern may be in contact with the first metal pattern and the second metal pattern, and the etch barrier pattern may be thinner than the first metal pattern and thinner than the second metal pattern.