Patents by Inventor Junrong Yan

Junrong Yan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11289395
    Abstract: A process includes forming one or more apertures on a component backside, creating a vacuum in a mold chase, and engaging the component backside with a mold compound in the mold chase. The one or more apertures form an aperture structure. The aperture structure may include multiple apertures parallel or orthogonal to each other. The apertures have an aperture width, aperture depth, and aperture pitch. These characteristics may be altered to minimize the likelihood of trapped air remaining after creating the vacuum in the mold chase.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: March 29, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Junrong Yan, Chee Keong Chin, Xin Lu
  • Publication number: 20220052014
    Abstract: A semiconductor device includes an integrated circuit die having bond pads and a bond wires. The bond wires are connected to respective ones of the bond pads by a ball bond. An area of contact between the ball bond and the bond pad has a predetermined shape that is non-circular and includes at least one axis of symmetry. A ratio of the ball bond length to the ball bond width may be equal to a ratio of the bond pad length to the bond pad width.
    Type: Application
    Filed: February 26, 2021
    Publication date: February 17, 2022
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yang Lei, Xiaofeng Di, Yuyun Lou, Zhonghua Qian, Junrong Yan
  • Patent number: 11240486
    Abstract: Discrete frequencies and time slots of operation are assigned to each of a plurality of time-of-flight cameras. Where two time-of-flight cameras having overlapping fields of view, whether the time-of-flight cameras are operating at the same frequency or time slot is determined by calculating ratios of zero-value pixels to total numbers of pixels for each depth image captured by the time-of-flight cameras over a selected interval. If the time-of-flight cameras operate at the same frequency or time slot, a plot of the ratios of depth images captured using one time-of-flight camera is erratically sinusoidal. Another time-of-flight camera causing the interference may be identified among time-of-flight cameras operating at the frequency or time slot, based on areas of interest that overlap with the time-of-flight camera, or based on a time at which the time-of-flight cameras began capturing depth images, as compared to a time at which the interference is observed.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: February 1, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Bo Chen, Venkata Sri Krishnakanth Pulla, Junrong Yan
  • Publication number: 20210407967
    Abstract: A semiconductor device package includes a mechanical support structure that provides mechanical support to a stack of dies, where the dies are laterally offset from each other. The support structure has a sloped surface that is disposed at a non-perpendicular and non-parallel angle to other surfaces of the mechanical support structure. Electrical contacts are disposed on the sloped surface of the mechanical support structure for electrically interfacing with the stacked dies and on a different surface of the mechanical support structure for electrically interfacing with a substrate.
    Type: Application
    Filed: November 30, 2020
    Publication date: December 30, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: XIANLU CUI, JUNRONG YAN, CHEEKEONG CHIN, ZHONGHUA QIAN
  • Publication number: 20210366875
    Abstract: A semiconductor device includes a vertical column of wire bonds on substrate contact fingers of the device. Semiconductor dies are mounted on a substrate, and electrically coupled to the substrate such that groups of semiconductor dies may have bond wires extending to the same contact finger on the substrate. By bonding those wires to the contact finger in a vertical column, as opposed to separate, side-by-side wire bonds on the contact finger, an area of the contact finger may be reduced.
    Type: Application
    Filed: December 30, 2020
    Publication date: November 25, 2021
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Xiaofeng Di, Junrong Yan, CheeKeong Chin, Weili Wang, Xin Lu, Qi Deng, Chaur Yang Ng, Cong Zhang, Chenlin Yang, Chin-Tien Chiu
  • Patent number: 11177241
    Abstract: A semiconductor device is disclosed including a die stack including a number of dies aligned with each other with respect to an axis, and a top die that is offset along the axis the to prevent die cracking.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: November 16, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Junrong Yan, Jianming Zhang, Min Zhao, Kailei Zhang, Chee Keong Chin, Kim Lee Bock
  • Publication number: 20210158370
    Abstract: According to some embodiments, a system may facilitate collaborative transaction processing associated with a supply chain having a first entity and a second entity. In particular, a first entity database may store electronic records including information associated with at least a portion of the supply chain, and a first entity communication port may exchange information via a distributed computer system. A first entity computer processor may retrieve from the first entity database the information associated with the at least a portion of the supply chain. A subset of information about the supply chain may be identified by the first entity computer processor as being of interest to the second entity. The identified subset of information about the supply chain may then be recorded via a secure, distributed transaction ledger.
    Type: Application
    Filed: August 31, 2017
    Publication date: May 27, 2021
    Inventors: Peter Koudall, Benjamin Edward Beckmann, Annarita Giani, John William Carbone, Joseph Salvo, Junrong Yan, Dan Yang, Patricia MacKenzie, Walter Yund
  • Publication number: 20210099997
    Abstract: The disclosure discloses a method for distributing pilot frequency in a massive antenna system, including: dividing a pilot frequency set into three sub sets that are intersecting with each other, and then dividing the users of each cell into a cell central user and a cell edge user. The cell central users use an intersection set of three pilot frequency sub sets. The cell edge users of all cells use a difference set, an intersection set and a union set of three pilot frequency sub sets according to a certain rule. When it is designing to implement the pilot resource distribution plan of the massive antenna system, three cells that are adjacent with each other in the system are used as a cluster, and a pilot frequency use plan of any one cluster may be designed according to the method proposed by the disclosure, and then the same design plan is applied to other clusters in the system, and then is adjusted according to the user distribution of each cluster and the business distribution circumstance thereof.
    Type: Application
    Filed: March 29, 2019
    Publication date: April 1, 2021
    Inventors: Fangmin XU, Junrong YAN, Rulong CHU, Xingbao OU
  • Publication number: 20200381401
    Abstract: A semiconductor device is disclosed including a die stack including a number of dies aligned with each other with respect to an axis, and a top die that is offset along the axis the to prevent die cracking.
    Type: Application
    Filed: March 10, 2020
    Publication date: December 3, 2020
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Junrong Yan, Jianming Zhang, Min Zhao, Kailei Zhang, Chee Keong Chin, Kim Lee Bock
  • Publication number: 20200335481
    Abstract: A process includes forming one or more apertures on a component backside, creating a vacuum in a mold chase, and engaging the component backside with a mold compound in the mold chase. The one or more apertures form an aperture structure. The aperture structure may include multiple apertures parallel or orthogonal to each other. The apertures have an aperture width, aperture depth, and aperture pitch. These characteristics may be altered to minimize the likelihood of trapped air remaining after creating the vacuum in the mold chase.
    Type: Application
    Filed: March 17, 2020
    Publication date: October 22, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Junrong Yan, Chee Keong Chin, Xin Lu
  • Patent number: 10681338
    Abstract: Discrete frequencies and time slots of operation are assigned to each of a plurality of time-of-flight cameras. Where two time-of-flight cameras having overlapping fields of view, whether the time-of-flight cameras are operating at the same frequency or time slot is determined by calculating ratios of zero-value pixels to total numbers of pixels for each depth image captured by the time-of-flight cameras over a selected interval. If the time-of-flight cameras operate at the same frequency or time slot, a plot of the ratios of depth images captured using one time-of-flight camera is erratically sinusoidal. Another time-of-flight camera causing the interference may be identified among time-of-flight cameras operating at the frequency or time slot, based on areas of interest that overlap with the time-of-flight camera, or based on a time at which the time-of-flight cameras began capturing depth images, as compared to a time at which the interference is observed.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: June 9, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Bo Chen, Venkata Sri Krishnakanth Pulla, Junrong Yan
  • Patent number: 10483239
    Abstract: A semiconductor device is disclosed including semiconductor die formed with a row of functional die bond pads and an adjacent row of dummy die bond pads. The functional die bond pads may be electrically connected to the integrated circuits formed within the semiconductor die. The dummy die bond pads may be formed in the scribe area of a semiconductor wafer from which the semiconductor die are formed, and are provided for wire bonding the semiconductor die within the semiconductor device.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: November 19, 2019
    Assignee: SanDisk Semiconductor (Shanghai) Co. Ltd.
    Inventors: Junrong Yan, Xiaofeng Di, Harjashan Singh, Gokul Kumar, Chee Keong Chin, Ming Xia Wu, Jian Bin Gu
  • Patent number: 10418334
    Abstract: A semiconductor die is disclosed including corner recesses to prevent cracking of the semiconductor die during fabrication. Prior to dicing the semiconductor die from the wafer, recesses may be formed in the wafer at corners between any pair of semiconductor die. The recesses may be formed by a laser or photolithographic processes in the kerf area between semiconductor die. Once formed, the corner recesses prevent cracking and damage to semiconductor die which could otherwise occur at the corners of adjacent semiconductor die as the adjacent semiconductor die move relative to each other during the backgrind process.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: September 17, 2019
    Assignee: SanDisk Semiconductor (Shanghai) Co. Ltd.
    Inventors: Hang Zhang, Weili Wang, Junrong Yan, Kim Lee Bock, Chee Keong Chin, Chong Un Tan, Xin Tian
  • Publication number: 20190236489
    Abstract: An industrial part modeling system may include a digital twin industrial part modeling platform containing a plurality of learning models, each learning model describing characteristics of an industrial part available to be incorporated into an industrial asset. The system may also include an application server platform and a user interface platform to receive an industrial part search or analysis requests from a user. The application server platform may receive information about the industrial part search or analysis request and execute at least one search or analysis algorithm to evaluate learning models in the digital twin industrial part modeling platform. Based on said evaluation, the application server platform may provide an industrial part search or analysis result report to the user. Moreover, the application server platform may automatically arrange for at least one of a search or analysis algorithm and a learning model to be updated based on interaction with the user.
    Type: Application
    Filed: January 30, 2018
    Publication date: August 1, 2019
    Inventors: Peter KOUDAL, Walter YUND, Annarita GIANI, Junrong YAN, Dan YANG, Benjamin Edward BECKMANN, Joseph SALVO, John William CARBONE, Robert BANKS, Patricia MACKENZIE
  • Patent number: 10283485
    Abstract: A semiconductor device is disclosed including semiconductor die stacked in a stepped, offset configuration, where die bond pads of semiconductor die on different levels are interconnected using one or more conductive bumps.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: May 7, 2019
    Assignee: SanDisk Semiconductor (Shanghai) Co. Ltd.
    Inventors: Junrong Yan, Xiaofeng Di, Chee Keong Chin, Kim Lee Bock, Mingxia Wu
  • Publication number: 20180337161
    Abstract: A semiconductor device is disclosed including semiconductor die stacked in a stepped, offset configuration, where die bond pads of semiconductor die on different levels are interconnected using one or more conductive bumps.
    Type: Application
    Filed: June 8, 2017
    Publication date: November 22, 2018
    Applicant: SANDISK SEMICONDUCTOR (SHANGHAI) CO., LTD.
    Inventors: Junrong Yan, Xiaofeng Di, Chee Keong Chin, Kim Lee Bock, Mingxia Wu
  • Patent number: 10128218
    Abstract: A semiconductor device is disclosed that is formed with die bond pads at an edge of the semiconductor die. The die bond pads may be formed partially in a kerf area between semiconductor die on a wafer. When the wafer is diced, the die bond pads are severed along their length, leaving a portion of the die bond pads exposed at an edge of the diced semiconductor die. Having die bond pads at the edge of the die minimizes the offset between die when stacked into a package.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: November 13, 2018
    Assignee: SanDisk Semiconductor (Shanghai) Co. Ltd.
    Inventors: Junrong Yan, Chee Keong Chin, Chong Un Tan, Ming Xia Wu, Kim Lee Bock, Shrikar Bhagath
  • Patent number: 10075216
    Abstract: Provided in the present invention is a method for avoiding downlink interference between an indoor DAS system and a small base station, the steps comprising: step 1: determining an initial access RU, and establishing a signal strength table; step 2: the DAS system, by means of the chosen RU, attempts to establish a downlink with UE 1, and detects the signal to interference plus noise ratio (SINR) value of the downlink signal of UE 1, and comparing same with a preset threshold value ?1; step 3: UE 1 maintains one or a plurality of RU downlinks assigned thereto by the DAS system, during the communication process continuously detects an SINR value at a set time interval, and on the basis of whether same is greater than ?1, ensures a corresponding service quality.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: September 11, 2018
    Assignee: SUNWAVE COMMUNICATIONS CO., LTD.
    Inventors: Peng Pan, Xin Chen, Junrong Yan, Yingbiao Yao
  • Publication number: 20180190621
    Abstract: A semiconductor device is disclosed including semiconductor die formed with a row of functional die bond pads and an adjacent row of dummy die bond pads. The functional die bond pads may be electrically connected to the integrated circuits formed within the semiconductor die. The dummy die bond pads may be formed in the scribe area of a semiconductor wafer from which the semiconductor die are formed, and are provided for wire bonding the semiconductor die within the semiconductor device.
    Type: Application
    Filed: February 28, 2018
    Publication date: July 5, 2018
    Applicant: SANDISK SEMICONDUCTOR (SHANGHAI) CO., LTD.
    Inventors: Junrong Yan, Xiaofeng Di, Harjashan Singh, Gokul Kumar, Chee Keong Chin, Ming Xia Wu, Jian Bin Gu
  • Publication number: 20180174983
    Abstract: A semiconductor die is disclosed including corner recesses to prevent cracking of the semiconductor die during fabrication. Prior to dicing the semiconductor die from the wafer, recesses may be formed in the wafer at corners between any pair of semiconductor die. The recesses may be formed by a laser or photolithographic processes in the kerf area between semiconductor die. Once formed, the corner recesses prevent cracking and damage to semiconductor die which could otherwise occur at the corners of adjacent semiconductor die as the adjacent semiconductor die move relative to each other during the backgrind process.
    Type: Application
    Filed: June 22, 2017
    Publication date: June 21, 2018
    Applicant: SANDISK SEMICONDUCTOR (SHANGHAI) CO., LTD.
    Inventors: Hang Zhang, Weili Wang, Junrong Yan, Kim Lee Bock, Chee Keong Chin, Chong Un Tan, Xin Tian