Abstract: A semiconductor device is disclosed including a die stack including a number of dies aligned with each other with respect to an axis, and a top die that is offset along the axis the to prevent die cracking.

Abstract: A process includes forming one or more apertures on a component backside, creating a vacuum in a mold chase, and engaging the component backside with a mold compound in the mold chase. The one or more apertures form an aperture structure. The aperture structure may include multiple apertures parallel or orthogonal to each other. The apertures have an aperture width, aperture depth, and aperture pitch. These characteristics may be altered to minimize the likelihood of trapped air remaining after creating the vacuum in the mold chase.

Abstract: Discrete frequencies and time slots of operation are assigned to each of a plurality of time-of-flight cameras. Where two time-of-flight cameras having overlapping fields of view, whether the time-of-flight cameras are operating at the same frequency or time slot is determined by calculating ratios of zero-value pixels to total numbers of pixels for each depth image captured by the time-of-flight cameras over a selected interval. If the time-of-flight cameras operate at the same frequency or time slot, a plot of the ratios of depth images captured using one time-of-flight camera is erratically sinusoidal. Another time-of-flight camera causing the interference may be identified among time-of-flight cameras operating at the frequency or time slot, based on areas of interest that overlap with the time-of-flight camera, or based on a time at which the time-of-flight cameras began capturing depth images, as compared to a time at which the interference is observed.

Abstract: A semiconductor device is disclosed including semiconductor die formed with a row of functional die bond pads and an adjacent row of dummy die bond pads. The functional die bond pads may be electrically connected to the integrated circuits formed within the semiconductor die. The dummy die bond pads may be formed in the scribe area of a semiconductor wafer from which the semiconductor die are formed, and are provided for wire bonding the semiconductor die within the semiconductor device.

Abstract: A semiconductor die is disclosed including corner recesses to prevent cracking of the semiconductor die during fabrication. Prior to dicing the semiconductor die from the wafer, recesses may be formed in the wafer at corners between any pair of semiconductor die. The recesses may be formed by a laser or photolithographic processes in the kerf area between semiconductor die. Once formed, the corner recesses prevent cracking and damage to semiconductor die which could otherwise occur at the corners of adjacent semiconductor die as the adjacent semiconductor die move relative to each other during the backgrind process.

Abstract: An industrial part modeling system may include a digital twin industrial part modeling platform containing a plurality of learning models, each learning model describing characteristics of an industrial part available to be incorporated into an industrial asset. The system may also include an application server platform and a user interface platform to receive an industrial part search or analysis requests from a user. The application server platform may receive information about the industrial part search or analysis request and execute at least one search or analysis algorithm to evaluate learning models in the digital twin industrial part modeling platform. Based on said evaluation, the application server platform may provide an industrial part search or analysis result report to the user. Moreover, the application server platform may automatically arrange for at least one of a search or analysis algorithm and a learning model to be updated based on interaction with the user.

Abstract: A semiconductor device is disclosed including semiconductor die stacked in a stepped, offset configuration, where die bond pads of semiconductor die on different levels are interconnected using one or more conductive bumps.

Abstract: A semiconductor device is disclosed including semiconductor die stacked in a stepped, offset configuration, where die bond pads of semiconductor die on different levels are interconnected using one or more conductive bumps.

Abstract: A semiconductor device is disclosed that is formed with die bond pads at an edge of the semiconductor die. The die bond pads may be formed partially in a kerf area between semiconductor die on a wafer. When the wafer is diced, the die bond pads are severed along their length, leaving a portion of the die bond pads exposed at an edge of the diced semiconductor die. Having die bond pads at the edge of the die minimizes the offset between die when stacked into a package.

Abstract: Provided in the present invention is a method for avoiding downlink interference between an indoor DAS system and a small base station, the steps comprising: step 1: determining an initial access RU, and establishing a signal strength table; step 2: the DAS system, by means of the chosen RU, attempts to establish a downlink with UE 1, and detects the signal to interference plus noise ratio (SINR) value of the downlink signal of UE 1, and comparing same with a preset threshold value ?1; step 3: UE 1 maintains one or a plurality of RU downlinks assigned thereto by the DAS system, during the communication process continuously detects an SINR value at a set time interval, and on the basis of whether same is greater than ?1, ensures a corresponding service quality.

Abstract: A semiconductor device is disclosed including semiconductor die formed with a row of functional die bond pads and an adjacent row of dummy die bond pads. The functional die bond pads may be electrically connected to the integrated circuits formed within the semiconductor die. The dummy die bond pads may be formed in the scribe area of a semiconductor wafer from which the semiconductor die are formed, and are provided for wire bonding the semiconductor die within the semiconductor device.

Abstract: A semiconductor die is disclosed including corner recesses to prevent cracking of the semiconductor die during fabrication. Prior to dicing the semiconductor die from the wafer, recesses may be formed in the wafer at corners between any pair of semiconductor die. The recesses may be formed by a laser or photolithographic processes in the kerf area between semiconductor die. Once formed, the corner recesses prevent cracking and damage to semiconductor die which could otherwise occur at the corners of adjacent semiconductor die as the adjacent semiconductor die move relative to each other during the backgrind process.

Abstract: A semiconductor device is disclosed that is formed with die bond pads at an edge of the semiconductor die. The die bond pads may be formed partially in a kerf area between semiconductor die on a wafer. When the wafer is diced, the die bond pads are severed along their length, leaving a portion of the die bond pads exposed at an edge of the diced semiconductor die. Having die bond pads at the edge of the die minimizes the offset between die when stacked into a package.

Abstract: The present invention provides a method for resisting small base station uplink signal interference of an indoor DAS based on antenna selection. The method comprises: step 1: determining an initial access RU, and establishing an uplink; step 2: determining, by the access RU of UE 1 on the basis of the level of interference, whether to switch to another RU, and continuously detecting, by the access RU of UE 1 an SINR value at a set time interval, and comparing the SINR with a preset threshold value ?1; wherein if the SINR value is lower than ?1, an MU sets the access RU and each peripheral RU as a candidate RU, and the MU, on the basis of the acquired SINR value of each RU, selects an SINR greater than ?1 and sets the RU having the greatest receiving signal power as the new access RU of UE 1.

Abstract: Provided in the present invention is a method for avoiding downlink interference between an indoor DAS system and a small base station, the steps comprising: step 1: determining an initial access RU, and establishing a signal strength table; step 2: the DAS system, by means of the chosen RU, attempts to establish a downlink with UE 1, and detects the signal to interference plus noise ratio (SINR) value of the downlink signal of UE 1, and comparing same with a preset threshold value ?1; step 3: UE 1 maintains one or a plurality of RU downlinks assigned thereto by the DAS system, during the communication process continuously detects an SINR value at a set time interval, and on the basis of whether same is greater than ?1, ensures a corresponding service quality.

Abstract: The present invention provides a method for resisting small base station uplink signal interference of an indoor DAS based on antenna selection. The method comprises: step 1: determining an initial access RU, and establishing an uplink; step 2: determining, by the access RU of UE 1 on the basis of the level of interference, whether to switch to another RU, and continuously detecting, by the access RU of UE 1 an SINR value at a set time interval, and comparing the SINR with a preset threshold value ?1; wherein if the SINR value is lower than ?1, an MU sets the access RU and each peripheral RU as a candidate RU, and the MU, on the basis of the acquired SINR value of each RU, selects an SINR greater than ?1 and sets the RU having the greatest receiving signal power as the new access RU of UE 1.

Abstract: A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a semiconductor die, such as a controller die, mounted on a surface of a substrate. A bridge structure is also mounted to the substrate, with the semiconductor die fitting within a trench formed in a bottom surface of the bridge structure. The bridge structure may be formed from a semiconductor wafer into either a dummy bridge structure functioning as a mechanical spacer layer, or an IC bridge structure functioning as both a mechanical spacer layer and an integrated circuit semiconductor die. Memory die may also be mounted atop the bridge structure.

Abstract: A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a semiconductor die, such as a controller die, mounted on a surface of a substrate. A spacer layer is also mounted to the substrate, with the semiconductor die fitting within an aperture or a notch formed through first and second major opposed surfaces of the spacer layer. Additional semiconductor die, such as flash memory die, may be mounted atop the spacer layer.

Abstract: A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a semiconductor die, such as a controller die, mounted on a surface of a substrate. A spacer layer is also mounted to the substrate, with the semiconductor die fitting within an aperture or a notch formed through first and second major opposed surfaces of the spacer layer. Additional semiconductor die, such as flash memory die, may be mounted atop the spacer layer.

Abstract: A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a semiconductor die, such as a controller die, mounted on a surface of a substrate. A bridge structure is also mounted to the substrate, with the semiconductor die fitting within a trench formed in a bottom surface of the bridge structure. The bridge structure may be formed from a semiconductor wafer into either a dummy bridge structure functioning as a mechanical spacer layer, or an IC bridge structure functioning as both a mechanical spacer layer and an integrated circuit semiconductor die. Memory die may also be mounted atop the bridge structure.