Patents by Inventor Junsheng CHEN
Junsheng CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240419355Abstract: Embodiments of the present disclosure provide a method, apparatus, electronic device and storage medium for storing data. After target data is obtained, a first data feature of the target data is extracted, the first data feature representing a data volume of the target data; the target shard number is obtained based on the first data feature, the target shard number representing the number of storage units for storing target data; a corresponding storage engine is obtained based on the target shard number, and the target data is stored in the storage engines in shards. The matched target shard number is obtained based on the first data feature of the target data, and a corresponding storage engine for storage is obtained based on the target shard number.Type: ApplicationFiled: June 7, 2024Publication date: December 19, 2024Inventors: Zhengwen CHEN, Junsheng TAN, Nan LI, Xiao CHEN, Yingju GAO, Dong WANG
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Publication number: 20240395219Abstract: A driving circuit, a display device and a driving method relate to the field of display technology. The driving circuit includes: an induction coil, a first switch module, a first control circuit and a second control circuit. An induction coil is configured for receiving a first radio frequency signal or a second radio frequency signal to supply power to a driving circuit; a first switch module is respectively connected to the induction coil, the first control circuit and the second control circuit, and is configured for conducting the induction coil and the first control circuit in a first state or conducting the induction coil and the second control circuit in a second state; a first control circuit is configured for performing data transmission with a first terminal in the first state; the first terminal is a terminal for transmitting a first radio frequency signal.Type: ApplicationFiled: July 20, 2022Publication date: November 28, 2024Applicants: CHONGQING BOE SMART ELECTRONICS SYSTEM CO., LTD., BOE Technology Group Co., Ltd.Inventors: Yunyan Xie, Lichun Chen, Xinbo Yu, Nanting Chen, Qiangeng Cheng, Junsheng Chen
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Patent number: 12150241Abstract: Disclosed is an antenna impedance matching circuit, an antenna system, a printed circuit board, and a terminal. The antenna impedance matching circuit comprises: a first transmission line having a first specific length such that the first transmission line is capacitive, and a second transmission line having a second specific length such that the second transmission line is inductive. In particular, the first transmission line and the second transmission line are connected in parallel, and terminals of the first transmission line and the second transmission line are open or shorted.Type: GrantFiled: December 18, 2019Date of Patent: November 19, 2024Assignee: HuiZhou TCL Mobile Communication Co., Ltd.Inventors: Wei Chen, Junsheng Hou, Song Bai
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Publication number: 20240336035Abstract: Provided are a chromium-free passivated and film-covered tinned plate, a passivation treatment solution for manufacturing a passivation film, and a manufacturing method for a tinned plate. The chromium-free passivated and film-covered tinned plate comprises a tinned plate and a polyester film laminated on a surface of the tinned plate. The tinned plate comprises a substrate, a tin coating and a passivation film covering a surface of the tin coating. The passivation film does not contain chromium, and contains 2.0-20 mg/m2 of zinc and 10-60 mg/m2 of silicon. A solvent in the passivation treatment solution is water, and the solution contains 0.5-5.0 wt % of a zinc salt and 10-30 wt % of an organosiloxane or a polysiloxane.Type: ApplicationFiled: October 12, 2022Publication date: October 10, 2024Inventors: Zhangwei Wang, Junsheng Wei, Peng Li, Hongxing Chen, Hua Ni
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Publication number: 20240264222Abstract: A design-for-test circuit for evaluating a BTI effect is disclosed, the DFT circuit comprises a plurality of stress generators having logic circuits with a plurality of input and output terminals. Each output terminal is connected to the grid of the device to be tested. In a stress mode, a stress input signal is selected from a frequency signal, a first direct current voltage, and a second direct current voltage, all stress output signals formed by all the stress generators comprise the first direct current voltage, a series of frequency signals with different duty cycles, and the second direct current voltage, and all the stress output signals are used in combination such that the stress times regarding the device under test within the same test time have a plurality of different values, so as to evaluate the BTI effect of the device under test having different values of the stress times.Type: ApplicationFiled: August 3, 2022Publication date: August 8, 2024Inventors: Zhenan Lai, Junsheng Chen
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Patent number: 12044723Abstract: A design-for-test circuit for evaluating a BTI effect is disclosed, the circuit includes a number of stress generators having logic circuits with input and output terminals. Each output terminal is connected to the grid of the device to be tested. In a stress mode, a stress input signal is selected from a frequency signal, a first direct current voltage, and a second direct current voltage, all stress output signals formed by all the stress generators comprise the first direct current voltage, a series of frequency signals with different duty cycles, and the second direct current voltage, and all the stress output signals are used in combination such that the stress times regarding the device under test within the same test time have different values, so as to evaluate the BTI effect of the device under test which has different values of the stress times.Type: GrantFiled: August 3, 2022Date of Patent: July 23, 2024Assignee: Shanghai Huali Integrated Circuit CorporationInventors: Zhenan Lai, Junsheng Chen
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Publication number: 20240192174Abstract: A modular wheeled mobile ultrasonic structure detection apparatus is disclosed, including a mobile detection platform, at least one ultrasonic detection roller, at least one ultrasonic sensor, and a steering balance mechanism including a connecting arm and at least one balancing apparatus; the balancing apparatus includes a balancing cylinder hinged to the connecting arm, a balancing spring provided in the balancing cylinder, and a steering linkage hinged to the mobile detection platform, a piston being connected to one end of the steering linkage away from the mobile detection platform and the balancing spring being in contact with the piston; and the piston can move along a length direction of the balancing cylinder and thereby define a direction of the steering linkage. When the structure surface fluctuates, bends, or turns, the mobile detection platform can rotate relative to the connecting arm to change the moving posture to adapt to various complex detection conditions.Type: ApplicationFiled: July 16, 2021Publication date: June 13, 2024Applicants: SOUTH CHINA UNIVERSITY OF TECHNOLOGY, TONGJI UNIVERSITYInventors: Renguo GU, Yingguang FANG, Hehua ZHU, Wei WU, Junsheng CHEN, Xiaobin DING
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Publication number: 20240077771Abstract: The present disclosure provides a display panel, including: a first panel and a second panel opposite to the first panel; the first panel includes: gate lines extending along a first direction and data lines extending along a second direction, and the gate lines and the data lines intersect to define pixel regions; the second panel includes: a plurality of support column periodic units arranged in an array along the first direction and the second direction, each support column periodic unit includes a plurality of support columns, and at least a part of the support columns each satisfy: a connection line between the support column and a support column closest thereto extends along a third direction, and an included angle between the third direction and the first direction is not equal to 0°. The present disclosure further provides a display device.Type: ApplicationFiled: November 29, 2021Publication date: March 7, 2024Inventors: Hui WANG, Yuqi LIU, Qianqian ZHANG, Yanni LIU, Yijun WANG, Sheng WANG, Junsheng CHEN
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Patent number: 11875715Abstract: The disclosure provides a shift register, a gate driving circuit and a display panel. The shift register includes: an input sub-circuit and a first output sub-circuit; the input sub-circuit pre-charges, in response to an input signal, a pull-up node by a first power voltage; the pull-up node is a coupling node at which the input sub-circuit and the output sub-circuit are coupled; the first output sub-circuit outputs a clock signal through a first signal output terminal in response to a potential of the pull-up node; the shift register further includes: a first noise reduction sub-circuit and/or a second noise reduction sub-circuit; the first noise reduction sub-circuit performs noise reduction on the pull-up node through a non-operation level signal in a blank period; the second noise reduction sub-circuit performs noise reduction on the first signal output terminal by the non-operation level signal during the blank period.Type: GrantFiled: December 29, 2020Date of Patent: January 16, 2024Assignees: HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Honggang Gu, Junsheng Chen, Jie Song
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Publication number: 20230410928Abstract: The present application discloses a design for testability circuit of an SRAM. In a write path circuit detection mode of a fault diagnosis logic control module, a write path circuit is in an on state, a write data bit multiplexer is in a selected state, a read data bit multiplexer is in a deselected state, a read path circuit is in an on state, and a memory cell is in a selected state; in a read path circuit detection mode, the write path circuit is in an off state, the write data bit multiplexer is in a selected state, the read data bit multiplexer is in a deselected state, the read path circuit is in an on state, and the memory cell is in a deselected state. A bit line signal end is connected to a test signal outputted by a signal generation circuit.Type: ApplicationFiled: February 22, 2023Publication date: December 21, 2023Applicant: Shanghai Huali Integrated Circuit CorporationInventors: Zhenan Lai, Junsheng Chen
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Publication number: 20230347702Abstract: The present invention discloses an adaptive damping nonlinear spring-variable damping system and a mobile platform system, with the nonlinear spring-variable damping system applied to the mobile platform. The nonlinear spring-variable damping system is characterized in that the system comprises: an oil cylinder accommodating damping oil; a piston, accommodated in the oil cylinder and movable along the oil cylinder to make the damping oil flow; at least one connecting rod, connected to the piston; at least one spring, whose deformation process is constrained by the connecting rod; and a damping adaptive adjustment device, configured to be able to adaptively change the flow resistance of the damping oil according to the vibration of the mobile platform, so as to control the system damping; wherein, when the mobile platform vibrates, the connecting rod and the spring can subject the piston to a nonlinear spring force.Type: ApplicationFiled: July 11, 2023Publication date: November 2, 2023Applicants: SOUTH CHINA UNIVERSITY OF TECHNOLOGY, TONGJI UNIVERSITYInventors: Yingguang FANG, Renguo GU, Hehua ZHU, Wei WU, Xiaobin DING, Junsheng CHEN
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Patent number: 11714307Abstract: A display device includes a backlight module; a display module located on a light exiting side of the backlight module; and a housing accommodating the backlight module and the display module. The display module includes a display panel including an array substrate and a color film substrate arranged opposite to each other. The color film substrate is located between the array substrate and the backlight module. A first polarizer located on one side of the array substrate away from the color film substrate. A manufacturing method of a display device is also provided.Type: GrantFiled: August 26, 2021Date of Patent: August 1, 2023Assignees: HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO, LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Jie Yang, Yuansheng Zang, Heng Zhang, Sheng Wang, Hui Wang, Junsheng Chen, Feng Qu, Yan Wang
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Publication number: 20230079961Abstract: A design-for-test circuit for evaluating a BTI effect is disclosed, the DFT circuit comprises a plurality of stress generators having logic circuits with a plurality of input and output terminals. Each output terminal is connected to the grid of the device to be tested. In a stress mode, a stress input signal is selected from a frequency signal, a first direct current voltage, and a second direct current voltage, all stress output signals formed by all the stress generators comprise the first direct current voltage, a series of frequency signals with different duty cycles, and the second direct current voltage, and all the stress output signals are used in combination such that the stress times regarding the device under test within the same test time have a plurality of different values, so as to evaluate the BTI effect of the device under test having different values of the stress times.Type: ApplicationFiled: August 3, 2022Publication date: March 16, 2023Inventors: Zhenan Lai, Junsheng Chen
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Publication number: 20230056588Abstract: A display device includes a backlight module; a display module located on a light exiting side of the backlight module; and a housing accommodating the backlight module and the display module. The display module includes a display panel including an array substrate and a color film substrate arranged opposite to each other. The color film substrate is located between the array substrate and the backlight module. A first polarizer located on one side of the array substrate away from the color film substrate. A manufacturing method of a display device is also provided.Type: ApplicationFiled: August 26, 2021Publication date: February 23, 2023Inventors: Jie Yang, Yuansheng Zang, Heng Zhang, Sheng Wang, Hui Wang, Junsheng Chen, Feng Qu, Yan Wang
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Patent number: 11535674Abstract: The present disclosure discloses a method for expressing and preparing a bivalent bispecific antibody. In the present disclosure, each portion of a bivalent bispecific antibody and an immune hybrid protein thereof is respectively expressed in a suitable prokaryotic or eukaryotic cell system, separated and purified by high-performance affinity chromatography, and then spliced in vitro by trans-splicing reaction mediated by an intein, to prepare the bivalent specific antibody and an immune hybrid protein thereof.Type: GrantFiled: December 16, 2016Date of Patent: December 27, 2022Assignees: SHANGHAI JIAO TONG UNIVERSITY, JECHO LABORATORIES INC., JECHO BIOPHARMACEUTICALS CO LTD.Inventors: Lei Han, Jianwei Zhu, Junsheng Chen, Kai Ding, Yueqing Xie, Hua Jiang, Huili Lu, Baohong Zhang, Lei Zhang
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Patent number: 11480823Abstract: An array substrate has a plurality of sub-pixel regions, and each sub-pixel region includes an opening region and a pixel defining region surrounding the opening region. The array substrate includes a base and a plurality of touch signal lines disposed on the base. An orthographic projection of at least one touch signal line on the base passes through, along an extending direction thereof, at least one opening region.Type: GrantFiled: December 13, 2019Date of Patent: October 25, 2022Assignees: HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.Inventors: Junsheng Chen, Hui Wang, Xianjie Shao
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Publication number: 20220335870Abstract: The disclosure provides a shift register, a gate driving circuit and a display panel. The shift register includes: an input sub-circuit and a first output sub-circuit; the input sub-circuit pre-charges, in response to an input signal, a pull-up node by a first power voltage; the pull-up node is a coupling node at which the input sub-circuit and the output sub circuit are coupled; the first output sub-circuit outputs a clock signal through a first signal output terminal in response to a potential of the pull-up node; the shift register further includes: a first noise reduction sub-circuit and/or a second noise reduction sub-circuit; the first noise reduction sub-circuit performs noise reduction on the pull-up node through a non-operation level signal in a blank period; the second noise reduction sub-circuit perform noise reduction on the first signal output terminal by the non-operation level signal during the blank period.Type: ApplicationFiled: December 29, 2020Publication date: October 20, 2022Inventors: Honggang GU, Junsheng CHEN, Jie SONG
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Publication number: 20220325286Abstract: Provided is a polypeptide combination, a targeting component thereof comprising a shielding peptide, a cleavable part, an antigen-binding part and a first intein fragment, the shielding peptide and the antigen-binding part being connected by means of the cleavable part, and the antigen-binding part being directly or indirectly connected to the first intein fragment; a toxin component thereof comprises a second intein fragment and a toxin, and the second intein fragment is directly or indirectly connected to the toxin; the targeting component and the toxin component form an immunoconjugate by means of the interactive action between the first intein fragment and the second intein fragment; in the immunoconjugate, the shielding peptide and the antigen-binding part are connected by means of the cleavable part, and the antigen-binding part is connected to the toxin. Also provided are a preparation method and a pharmaceutical use for the polypeptide combination.Type: ApplicationFiled: April 20, 2020Publication date: October 13, 2022Applicants: SHANGHAI JIAO TONG UNIVERSITY, JECHO LABORATORIES, INC.Inventors: Jianwei ZHU, Jing WANG, Junsheng CHEN, Yueqing XIE, Hua JIANG, Huifang ZONG, Lei HAN
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Patent number: 11462290Abstract: The disclosure discloses a wafer acceptance test module for a static memory function test, reduced instruction built-in self-test circuit formed on a wafer includes: a ring oscillator, a frequency divider, a counter, a data latch and comparator. The counter is used for count, and the count is used as an input signal of each of an address decoder and a data input port at the same time. The data latch and comparator is connected to an output terminal of the address decoder and an output terminal of the sense amplifier and compare two output signals to obtain a test result. The disclosure also discloses a wafer acceptance test method for a static memory function test. The disclosure does not need to rely on a dedicated test machine for memory to perform a static memory function test, which can simplify a test procedure.Type: GrantFiled: June 15, 2020Date of Patent: October 4, 2022Assignee: Shanghai Huali Integrated Circuit CorporationInventors: Zhenan Lai, Junsheng Chen, Zhaoying Huang
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Publication number: 20220282231Abstract: A polypeptide composition, and methods of making the same, may include a first polypeptide and a second polypeptide, wherein the first polypeptide comprise a first toxin fragment and a first intein fragment, the second polypeptide comprise a second toxin fragment and a second intein fragment, the first polypeptide is different from the second polypeptide; the first toxin fragment and the second toxin fragment are non-biotoxic; the first polypeptide and the second polypeptide may make the first toxin fragment and the second toxin fragment into biotoxic toxins by means of the interaction of the first intein fragment and the second intein fragment. Kits may include such first and second polypeptides, and such compositions and kits may be used in treating tumors.Type: ApplicationFiled: September 27, 2019Publication date: September 8, 2022Applicants: SHANGHAI JIAO TONG UNIVERSITY, JECHO LABORATORIES, INC.Inventors: Jianwei ZHU, Jing WANG, Lei HAN, Junsheng CHEN, Yueqing XIE, Hua JIANG