Abstract: The present disclosure provides a display panel, including: a first panel and a second panel opposite to the first panel; the first panel includes: gate lines extending along a first direction and data lines extending along a second direction, and the gate lines and the data lines intersect to define pixel regions; the second panel includes: a plurality of support column periodic units arranged in an array along the first direction and the second direction, each support column periodic unit includes a plurality of support columns, and at least a part of the support columns each satisfy: a connection line between the support column and a support column closest thereto extends along a third direction, and an included angle between the third direction and the first direction is not equal to 0°. The present disclosure further provides a display device.

Abstract: The disclosure provides a shift register, a gate driving circuit and a display panel. The shift register includes: an input sub-circuit and a first output sub-circuit; the input sub-circuit pre-charges, in response to an input signal, a pull-up node by a first power voltage; the pull-up node is a coupling node at which the input sub-circuit and the output sub-circuit are coupled; the first output sub-circuit outputs a clock signal through a first signal output terminal in response to a potential of the pull-up node; the shift register further includes: a first noise reduction sub-circuit and/or a second noise reduction sub-circuit; the first noise reduction sub-circuit performs noise reduction on the pull-up node through a non-operation level signal in a blank period; the second noise reduction sub-circuit performs noise reduction on the first signal output terminal by the non-operation level signal during the blank period.

Abstract: The present application discloses a design for testability circuit of an SRAM. In a write path circuit detection mode of a fault diagnosis logic control module, a write path circuit is in an on state, a write data bit multiplexer is in a selected state, a read data bit multiplexer is in a deselected state, a read path circuit is in an on state, and a memory cell is in a selected state; in a read path circuit detection mode, the write path circuit is in an off state, the write data bit multiplexer is in a selected state, the read data bit multiplexer is in a deselected state, the read path circuit is in an on state, and the memory cell is in a deselected state. A bit line signal end is connected to a test signal outputted by a signal generation circuit.

Abstract: The present invention discloses an adaptive damping nonlinear spring-variable damping system and a mobile platform system, with the nonlinear spring-variable damping system applied to the mobile platform. The nonlinear spring-variable damping system is characterized in that the system comprises: an oil cylinder accommodating damping oil; a piston, accommodated in the oil cylinder and movable along the oil cylinder to make the damping oil flow; at least one connecting rod, connected to the piston; at least one spring, whose deformation process is constrained by the connecting rod; and a damping adaptive adjustment device, configured to be able to adaptively change the flow resistance of the damping oil according to the vibration of the mobile platform, so as to control the system damping; wherein, when the mobile platform vibrates, the connecting rod and the spring can subject the piston to a nonlinear spring force.

Abstract: A display device includes a backlight module; a display module located on a light exiting side of the backlight module; and a housing accommodating the backlight module and the display module. The display module includes a display panel including an array substrate and a color film substrate arranged opposite to each other. The color film substrate is located between the array substrate and the backlight module. A first polarizer located on one side of the array substrate away from the color film substrate. A manufacturing method of a display device is also provided.

Abstract: A design-for-test circuit for evaluating a BTI effect is disclosed, the DFT circuit comprises a plurality of stress generators having logic circuits with a plurality of input and output terminals. Each output terminal is connected to the grid of the device to be tested. In a stress mode, a stress input signal is selected from a frequency signal, a first direct current voltage, and a second direct current voltage, all stress output signals formed by all the stress generators comprise the first direct current voltage, a series of frequency signals with different duty cycles, and the second direct current voltage, and all the stress output signals are used in combination such that the stress times regarding the device under test within the same test time have a plurality of different values, so as to evaluate the BTI effect of the device under test having different values of the stress times.

Abstract: A display device includes a backlight module; a display module located on a light exiting side of the backlight module; and a housing accommodating the backlight module and the display module. The display module includes a display panel including an array substrate and a color film substrate arranged opposite to each other. The color film substrate is located between the array substrate and the backlight module. A first polarizer located on one side of the array substrate away from the color film substrate. A manufacturing method of a display device is also provided.

Abstract: The present disclosure discloses a method for expressing and preparing a bivalent bispecific antibody. In the present disclosure, each portion of a bivalent bispecific antibody and an immune hybrid protein thereof is respectively expressed in a suitable prokaryotic or eukaryotic cell system, separated and purified by high-performance affinity chromatography, and then spliced in vitro by trans-splicing reaction mediated by an intein, to prepare the bivalent specific antibody and an immune hybrid protein thereof.

Abstract: An array substrate has a plurality of sub-pixel regions, and each sub-pixel region includes an opening region and a pixel defining region surrounding the opening region. The array substrate includes a base and a plurality of touch signal lines disposed on the base. An orthographic projection of at least one touch signal line on the base passes through, along an extending direction thereof, at least one opening region.

Abstract: The disclosure provides a shift register, a gate driving circuit and a display panel. The shift register includes: an input sub-circuit and a first output sub-circuit; the input sub-circuit pre-charges, in response to an input signal, a pull-up node by a first power voltage; the pull-up node is a coupling node at which the input sub-circuit and the output sub circuit are coupled; the first output sub-circuit outputs a clock signal through a first signal output terminal in response to a potential of the pull-up node; the shift register further includes: a first noise reduction sub-circuit and/or a second noise reduction sub-circuit; the first noise reduction sub-circuit performs noise reduction on the pull-up node through a non-operation level signal in a blank period; the second noise reduction sub-circuit perform noise reduction on the first signal output terminal by the non-operation level signal during the blank period.

Abstract: Provided is a polypeptide combination, a targeting component thereof comprising a shielding peptide, a cleavable part, an antigen-binding part and a first intein fragment, the shielding peptide and the antigen-binding part being connected by means of the cleavable part, and the antigen-binding part being directly or indirectly connected to the first intein fragment; a toxin component thereof comprises a second intein fragment and a toxin, and the second intein fragment is directly or indirectly connected to the toxin; the targeting component and the toxin component form an immunoconjugate by means of the interactive action between the first intein fragment and the second intein fragment; in the immunoconjugate, the shielding peptide and the antigen-binding part are connected by means of the cleavable part, and the antigen-binding part is connected to the toxin. Also provided are a preparation method and a pharmaceutical use for the polypeptide combination.

Abstract: The disclosure discloses a wafer acceptance test module for a static memory function test, reduced instruction built-in self-test circuit formed on a wafer includes: a ring oscillator, a frequency divider, a counter, a data latch and comparator. The counter is used for count, and the count is used as an input signal of each of an address decoder and a data input port at the same time. The data latch and comparator is connected to an output terminal of the address decoder and an output terminal of the sense amplifier and compare two output signals to obtain a test result. The disclosure also discloses a wafer acceptance test method for a static memory function test. The disclosure does not need to rely on a dedicated test machine for memory to perform a static memory function test, which can simplify a test procedure.

Abstract: A polypeptide composition, and methods of making the same, may include a first polypeptide and a second polypeptide, wherein the first polypeptide comprise a first toxin fragment and a first intein fragment, the second polypeptide comprise a second toxin fragment and a second intein fragment, the first polypeptide is different from the second polypeptide; the first toxin fragment and the second toxin fragment are non-biotoxic; the first polypeptide and the second polypeptide may make the first toxin fragment and the second toxin fragment into biotoxic toxins by means of the interaction of the first intein fragment and the second intein fragment. Kits may include such first and second polypeptides, and such compositions and kits may be used in treating tumors.

Abstract: A display substrate, a display panel, a display device and a manufacturing method thereof are provided. The display substrate includes a display area and a non-display area. The display substrate further includes a base substrate; and a color resist layer and a light reflecting layer sequentially arranged on the non-display area of a first surface of the base substrate, wherein the first surface and a second surface of the base substrate are two surfaces opposite to each other and the second surface is located at a light exiting side of the display substrate.

Abstract: The present application discloses a mutual capacitive touch substrate having a matrix of a plurality of touch electrode blocks along a first direction and a second direction. The plurality of touch electrode blocks are grouped into a plurality of touch control repeating units. Each of the plurality of touch control repeating units includes a touch sensing electrode, one or more first touch scanning electrodes on a first side of the touch sensing electrode, and one or more second touch scanning electrodes on a second side of the touch sensing electrode, the first side is different from the second side. The touch sensing electrode abuts at least a portion of each of the one or more first touch scanning electrodes and at least a portion of each of the one or more second touch scanning electrodes. The plurality of touch control repeating units are electrically insulated from each other.

Abstract: A display substrate, a display panel, a display device and a manufacturing method thereof are provided. The display substrate includes a display area and a non-display area. The display substrate further includes a base substrate; and a color resist layer and a light reflecting layer sequentially arranged on the non-display area of a first surface of the base substrate, wherein the first surface and a second surface of the base substrate are two surfaces opposite to each other and the second surface is located at a light exiting side of the display substrate.

Abstract: The present disclosure provides a fingerprint identification touch panel and a display device and belongs to the field of display technology. The fingerprint identification touch panel includes: a fingerprint identification substrate disposed on a side of light-exiting surface of a display module; and a fingerprint identification chip configured to be electrically coupled with the fingerprint identification substrate and to identify fingerprint information according to a detection signal of the fingerprint identification substrate, where an orthographic projection of the fingerprint identification substrate on the display module does not overlap an orthographic projection of the fingerprint identification chip on the display module.

Abstract: The present application discloses a mutual capacitive touch substrate having a matrix of a plurality of touch electrode blocks along a first direction and a second direction. The plurality of touch electrode blocks are grouped into a plurality of touch control repeating units. Each of the plurality of touch control repeating units includes a touch sensing electrode, one or more first touch scanning electrodes on a first side of the touch sensing electrode, and one or more second touch scanning electrodes on a second side of the touch sensing electrode, the first side is different from the second side. The touch sensing electrode abuts at least a portion of each of the one or more first touch scanning electrodes and at least a portion of each of the one or more second touch scanning electrodes. The plurality of touch control repeating units are electrically insulated from each other.

Abstract: A shift register, a gate driving circuit, a display device, and a driving method of a node sustaining circuit are disclosed. The shift register includes an input sub-circuit, a reset sub-circuit, an output sub-circuit, a pull-down sub-circuit, a first control sub-circuit, a second control sub-circuit, a first storage sub-circuit, and a node sustaining circuit. The node sustaining circuit is configured to sustain the potential of a node, which is one of a pull-up node or a pull-down node in the shift register.

Abstract: The disclosure discloses a wafer acceptance test module for a static memory function test, reduced instruction built-in self-test circuit formed on a wafer includes: a ring oscillator, a frequency divider, a counter, a data latch and comparator. The counter is used for count, and the count is used as an input signal of each of an address decoder and a data input port at the same time. The data latch and comparator is connected to an output terminal of the address decoder and an output terminal of the sense amplifier and compare two output signals to obtain a test result. The disclosure also discloses a wafer acceptance test method for a static memory function test. The disclosure does not need to rely on a dedicated test machine for memory to perform a static memory function test, which can simplify a test procedure.