Patents by Inventor Junyeong HEO
Junyeong HEO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935832Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, and a side surface between the first and second surfaces, and including a device region on the first surface a wiring structure on the surface of the semiconductor substrate, and having a dielectric layer and a metal wiring in the dielectric layer and electrically connected to the device region, and an insulating material layer on a side surface of the wiring structure and having a side surface connected to the side surface of the semiconductor substrate. The side surface of the insulating material layer has a first wave-shaped pattern in which concave-convex portions are repeated in a direction of the wiring structure that is perpendicular to the semiconductor substrate, and the side surface of the semiconductor substrate has a second wave-shaped pattern in which concave-convex portions are repeated in the direction.Type: GrantFiled: October 6, 2022Date of Patent: March 19, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Junyeong Heo, Unbyoung Kang, Donghoon Won
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Patent number: 11869821Abstract: A semiconductor package includes: a first semiconductor chip including a first surface and a second surface opposite to each other and including first through electrodes; at least a second semiconductor chip stacked on the first surface of the first semiconductor chip and comprising second through electrodes electrically connected to the first through electrodes; and a molding layer contacting the first surface of the first semiconductor chip and a side wall of the at least one second semiconductor chip and including a first external side wall connected to and on the same plane as a side wall of the first semiconductor chip, wherein the first external side wall of the molding layer extends to be inclined with respect to a first direction orthogonal to the first surface of the first semiconductor chip, and both the external first side wall of the molding layer and the side wall of the first semiconductor chip have a first slope that is the same for both the first external side wall of the molding layer and theType: GrantFiled: August 2, 2022Date of Patent: January 9, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yeongkwon Ko, Seunghun Shin, Junyeong Heo
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Publication number: 20230326863Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, a plurality of semiconductor elements disposed on the first surface in a device region, an insulating protective layer, and a connection pad. The second surface is divided into a first region overlapping the device region, and a second region surrounding the first region. The insulating protective layer is disposed on the second surface of the semiconductor substrate, and includes an edge pattern positioned in the second region. The edge pattern includes a thinner portion having a thickness smaller than a thickness of a center portion of the insulating protective layer positioned in the first region and/or an open region exposing the second surface of the semiconductor substrate. The connection pad is disposed on the center portion of the insulating protective layer and is electrically connected to the semiconductor elements.Type: ApplicationFiled: June 2, 2023Publication date: October 12, 2023Inventors: YEONGKWON KO, JAEEUN LEE, JUNYEONG HEO
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Patent number: 11721669Abstract: A semiconductor package is provided including a first semiconductor chip stack and a second semiconductor chip stack that are adjacent to each other. The first semiconductor chip stack includes a plurality of first semiconductor chips and a plurality of first adhesive layers. The second semiconductor chip stack includes a plurality of second semiconductor chips and a plurality of second adhesive layers. Each of the first semiconductor chips includes a first cell region and a first scribe lane that surrounds the first cell region. Each of the second semiconductor chips includes a second cell region and a second scribe lane that surrounds the second cell region. An area of the first scribe lane is greater than an area of the second scribe lane. The plurality of first adhesive layers and the plurality of second adhesive layers have the same coefficient of thermal expansion.Type: GrantFiled: May 18, 2020Date of Patent: August 8, 2023Assignee: SAMSUNG ELECTRONICS CO, LTD.Inventors: Junyeong Heo, Jae-Eun Lee, Yeongkwon Ko, Donghoon Won
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Patent number: 11694963Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, a plurality of semiconductor elements disposed on the first surface in a device region, an insulating protective layer, and a connection pad. The second surface is divided into a first region overlapping the device region, and a second region surrounding the first region. The insulating protective layer is disposed on the second surface of the semiconductor substrate, and includes an edge pattern positioned in the second region. The edge pattern includes a thinner portion having a thickness smaller than a thickness of a center portion of the insulating protective layer positioned in the first region and/or an open region exposing the second surface of the semiconductor substrate. The connection pad is disposed on the center portion of the insulating protective layer and is electrically connected to the semiconductor elements.Type: GrantFiled: January 31, 2022Date of Patent: July 4, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yeongkwon Ko, Jaeeun Lee, Junyeong Heo
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Publication number: 20230065076Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.Type: ApplicationFiled: November 10, 2022Publication date: March 2, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Yeongkwon KO, Seunghun Shin, Junyeong Heo
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Publication number: 20230034015Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, and a side surface between the first and second surfaces, and including a device region on the first surface a wiring structure on the surface of the semiconductor substrate, and having a dielectric layer and a metal wiring in the dielectric layer and electrically connected to the device region, and an insulating material layer on a side surface of the wiring structure and having a side surface connected to the side surface of the semiconductor substrate. The side surface of the insulating material layer has a first wave-shaped pattern in which concave-convex portions are repeated in a direction of the wiring structure that is perpendicular to the semiconductor substrate, and the side surface of the semiconductor substrate has a second wave-shaped pattern in which concave-convex portions are repeated in the direction.Type: ApplicationFiled: October 6, 2022Publication date: February 2, 2023Inventors: Junyeong HEO, Unbyoung KANG, Donghoon WON
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Publication number: 20220399311Abstract: A semiconductor package includes a first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, and an insulating adhesive layer between the first semiconductor chip, and each of the plurality of second semiconductor chips, each of the plurality second conductor chips, and the insulating adhesive layer including an adhesive fillet protruding from between at least the first semiconductor chip and each of the plurality of second semiconductor chips, wherein a grooving recess is defined by the first semiconductor chip, the plurality of second semiconductor chips, and the insulating adhesive layer, the grooving recess including a first recess and a second recess adjacent to the first recess, an uppermost surface of the adhesive fillet and the first semiconductor chip defines the first recess, and an uppermost surface of the first semiconductor chip to a surface inside the first semiconductor chip defines the second recess.Type: ApplicationFiled: February 9, 2022Publication date: December 15, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Junyeong HEO, Yeongkwon KO, Unbyoung KANG, Teakhoon LEE
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Patent number: 11515226Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.Type: GrantFiled: December 10, 2020Date of Patent: November 29, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Yeongkwon Ko, Seunghun Shin, Junyeong Heo
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Publication number: 20220375808Abstract: A semiconductor package includes: a first semiconductor chip including a first surface and a second surface opposite to each other and including first through electrodes; at least a second semiconductor chip stacked on the first surface of the first semiconductor chip and comprising second through electrodes electrically connected to the first through electrodes; and a molding layer contacting the first surface of the first semiconductor chip and a side wall of the at least one second semiconductor chip and including a first external side wall connected to and on the same plane as a side wall of the first semiconductor chip, wherein the first external side wall of the molding layer extends to be inclined with respect to a first direction orthogonal to the first surface of the first semiconductor chip, and both the external first side wall of the molding layer and the side wall of the first semiconductor chip have a first slope that is the same for both the first external side wall of the molding layer and theType: ApplicationFiled: August 2, 2022Publication date: November 24, 2022Inventors: Yeongkwon Ko, Seunghun Shin, Junyeong Heo
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Patent number: 11469180Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, and a side surface between the first and second surfaces, and including a device region on the first surface a wiring structure on the surface of the semiconductor substrate, and having a dielectric layer and a metal wiring in the dielectric layer and electrically connected to the device region, and an insulating material layer on a side surface of the wiring structure and having a side surface connected to the side surface of the semiconductor substrate. The side surface of the insulating material layer has a first wave-shaped pattern in which concave-convex portions are repeated in a direction of the wiring structure that is perpendicular to the semiconductor substrate, and the side surface of the semiconductor substrate has a second wave-shaped pattern in which concave-convex portions are repeated in the direction.Type: GrantFiled: May 28, 2020Date of Patent: October 11, 2022Inventors: Junyeong Heo, Unbyoung Kang, Donghoon Won
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Patent number: 11424172Abstract: A semiconductor package includes: a first semiconductor chip including a first surface and a second surface opposite to each other and including first through electrodes; at least a second semiconductor chip stacked on the first surface of the first semiconductor chip and comprising second through electrodes electrically connected to the first through electrodes; and a molding layer contacting the first surface of the first semiconductor chip and a side wall of the at least one second semiconductor chip and including a first external side wall connected to and on the same plane as a side wall of the first semiconductor chip, wherein the first external side wall of the molding layer extends to be inclined with respect to a first direction orthogonal to the first surface of the first semiconductor chip, and both the external first side wall of the molding layer and the side wall of the first semiconductor chip have a first slope that is the same for both the first external side wall of the molding layer and theType: GrantFiled: January 5, 2021Date of Patent: August 23, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yeongkwon Ko, Seunghun Shin, Junyeong Heo
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Publication number: 20220157731Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, a plurality of semiconductor elements disposed on the first surface in a device region, an insulating protective layer, and a connection pad. The second surface is divided into a first region overlapping the device region, and a second region surrounding the first region. The insulating protective layer is disposed on the second surface of the semiconductor substrate, and includes an edge pattern positioned in the second region. The edge pattern includes a thinner portion having a thickness smaller than a thickness of a center portion of the insulating protective layer positioned in the first region and/or an open region exposing the second surface of the semiconductor substrate. The connection pad is disposed on the center portion of the insulating protective layer and is electrically connected to the semiconductor elements.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Inventors: YEONGKWON KO, JAEEUN LEE, JUNYEONG HEO
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Patent number: 11239171Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, a plurality of semiconductor elements disposed on the first surface in a device region, an insulating protective layer, and a connection pad. The second surface is divided into a first region overlapping the device region, and a second region surrounding the first region. The insulating protective layer is disposed on the second surface of the semiconductor substrate, and includes an edge pattern positioned in the second region. The edge pattern includes a thinner portion having a thickness smaller than a thickness of a center portion of the insulating protective layer positioned in the first region and/or an open region exposing the second surface of the semiconductor substrate. The connection pad is disposed on the center portion of the insulating protective layer and is electrically connected to the semiconductor elements.Type: GrantFiled: July 7, 2020Date of Patent: February 1, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yeongkwon Ko, Jaeeun Lee, Junyeong Heo
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Publication number: 20210375709Abstract: A semiconductor package includes: a first semiconductor chip including a first surface and a second surface opposite to each other and including first through electrodes; at least a second semiconductor chip stacked on the first surface of the first semiconductor chip and comprising second through electrodes electrically connected to the first through electrodes; and a molding layer contacting the first surface of the first semiconductor chip and a side wall of the at least one second semiconductor chip and including a first external side wall connected to and on the same plane as a side wall of the first semiconductor chip, wherein the first external side wall of the molding layer extends to be inclined with respect to a first direction orthogonal to the first surface of the first semiconductor chip, and both the external first side wall of the molding layer and the side wall of the first semiconductor chip have a first slope that is the same for both the first external side wall of the molding layer and theType: ApplicationFiled: January 5, 2021Publication date: December 2, 2021Inventors: Yeongkwon Ko, Seunghun Shin, Junyeong Heo
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Publication number: 20210343613Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.Type: ApplicationFiled: December 10, 2020Publication date: November 4, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Yeongkwon KO, Seunghun SHIN, Junyeong HEO
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Publication number: 20210143102Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, a plurality of semiconductor elements disposed on the first surface in a device region, an insulating protective layer, and a connection pad. The second surface is divided into a first region overlapping the device region, and a second region surrounding the first region. The insulating protective layer is disposed on the second surface of the semiconductor substrate, and includes an edge pattern positioned in the second region. The edge pattern includes a thinner portion having a thickness smaller than a thickness of a center portion of the insulating protective layer positioned in the first region and/or an open region exposing the second surface of the semiconductor substrate. The connection pad is disposed on the center portion of the insulating protective layer and is electrically connected to the semiconductor elements.Type: ApplicationFiled: July 7, 2020Publication date: May 13, 2021Inventors: YEONGKWON KO, JAEEUN LEE, JUNYEONG HEO
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Publication number: 20210125925Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, and a side surface between the first and second surfaces, and including a device region on the first surface a wiring structure on the surface of the semiconductor substrate, and having a dielectric layer and a metal wiring in the dielectric layer and electrically connected to the device region, and an insulating material layer on a side surface of the wiring structure and having a side surface connected to the side surface of the semiconductor substrate. The side surface of the insulating material layer has a first wave-shaped pattern in which concave-convex portions are repeated in a direction of the wiring structure that is perpendicular to the semiconductor substrate, and the side surface of the semiconductor substrate has a second wave-shaped pattern in which concave-convex portions are repeated in the direction.Type: ApplicationFiled: May 28, 2020Publication date: April 29, 2021Inventors: Junyeong HEO, Unbyoung KANG, Donghoon WON
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Publication number: 20210091045Abstract: A semiconductor package is provided including a first semiconductor chip stack and a second semiconductor chip stack that are adjacent to each other. The first semiconductor chip stack includes a plurality of first semiconductor chips and a plurality of first adhesive layers. The second semiconductor chip stack includes a plurality of second semiconductor chips and a plurality of second adhesive layers. Each of the first semiconductor chips includes a first cell region and a first scribe lane that surrounds the first cell region. Each of the second semiconductor chips includes a second cell region and a second scribe lane that surrounds the second cell region. An area of the first scribe lane is greater than an area of the second scribe lane. The plurality of first adhesive layers and the plurality of second adhesive layers have the same coefficient of thermal expansion.Type: ApplicationFiled: May 18, 2020Publication date: March 25, 2021Inventors: JUNYEONG HEO, JAE-EUN LEE, YEONGKWON KO, DONGHOON WON
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Publication number: 20210050264Abstract: There is provided a method of dicing a semiconductor wafer, which includes providing a semiconductor substrate having a plurality of integrated circuit regions on an active surface of the semiconductor substrate, a dicing regions provided between adjacent integrated circuit regions of the plurality of integrated circuit regions, and a metal shield layer provided on the active surface across at least a portion of the adjacent integrated circuit regions and the dicing region, forming a modified layer by irradiating laser to an inside of the semiconductor substrate along the dicing region, propagating a crack from the modified layer in a direction perpendicular to a major-axial direction of the metal shield layer by polishing an inactive surface opposing the active surface of the semiconductor substrate and forming semiconductor chips by separating the adjacent integrated circuit regions, respectively, based on the crack propagating from the modified layer.Type: ApplicationFiled: May 11, 2020Publication date: February 18, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Donghoon WON, Jaeeun Lee, Yeongkwon Ko, Junyeong Heo