Patents by Inventor Junyeong HEO

Junyeong HEO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11239171
    Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, a plurality of semiconductor elements disposed on the first surface in a device region, an insulating protective layer, and a connection pad. The second surface is divided into a first region overlapping the device region, and a second region surrounding the first region. The insulating protective layer is disposed on the second surface of the semiconductor substrate, and includes an edge pattern positioned in the second region. The edge pattern includes a thinner portion having a thickness smaller than a thickness of a center portion of the insulating protective layer positioned in the first region and/or an open region exposing the second surface of the semiconductor substrate. The connection pad is disposed on the center portion of the insulating protective layer and is electrically connected to the semiconductor elements.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: February 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yeongkwon Ko, Jaeeun Lee, Junyeong Heo
  • Publication number: 20210375709
    Abstract: A semiconductor package includes: a first semiconductor chip including a first surface and a second surface opposite to each other and including first through electrodes; at least a second semiconductor chip stacked on the first surface of the first semiconductor chip and comprising second through electrodes electrically connected to the first through electrodes; and a molding layer contacting the first surface of the first semiconductor chip and a side wall of the at least one second semiconductor chip and including a first external side wall connected to and on the same plane as a side wall of the first semiconductor chip, wherein the first external side wall of the molding layer extends to be inclined with respect to a first direction orthogonal to the first surface of the first semiconductor chip, and both the external first side wall of the molding layer and the side wall of the first semiconductor chip have a first slope that is the same for both the first external side wall of the molding layer and the
    Type: Application
    Filed: January 5, 2021
    Publication date: December 2, 2021
    Inventors: Yeongkwon Ko, Seunghun Shin, Junyeong Heo
  • Publication number: 20210343613
    Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.
    Type: Application
    Filed: December 10, 2020
    Publication date: November 4, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yeongkwon KO, Seunghun SHIN, Junyeong HEO
  • Publication number: 20210143102
    Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, a plurality of semiconductor elements disposed on the first surface in a device region, an insulating protective layer, and a connection pad. The second surface is divided into a first region overlapping the device region, and a second region surrounding the first region. The insulating protective layer is disposed on the second surface of the semiconductor substrate, and includes an edge pattern positioned in the second region. The edge pattern includes a thinner portion having a thickness smaller than a thickness of a center portion of the insulating protective layer positioned in the first region and/or an open region exposing the second surface of the semiconductor substrate. The connection pad is disposed on the center portion of the insulating protective layer and is electrically connected to the semiconductor elements.
    Type: Application
    Filed: July 7, 2020
    Publication date: May 13, 2021
    Inventors: YEONGKWON KO, JAEEUN LEE, JUNYEONG HEO
  • Publication number: 20210125925
    Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, and a side surface between the first and second surfaces, and including a device region on the first surface a wiring structure on the surface of the semiconductor substrate, and having a dielectric layer and a metal wiring in the dielectric layer and electrically connected to the device region, and an insulating material layer on a side surface of the wiring structure and having a side surface connected to the side surface of the semiconductor substrate. The side surface of the insulating material layer has a first wave-shaped pattern in which concave-convex portions are repeated in a direction of the wiring structure that is perpendicular to the semiconductor substrate, and the side surface of the semiconductor substrate has a second wave-shaped pattern in which concave-convex portions are repeated in the direction.
    Type: Application
    Filed: May 28, 2020
    Publication date: April 29, 2021
    Inventors: Junyeong HEO, Unbyoung KANG, Donghoon WON
  • Publication number: 20210091045
    Abstract: A semiconductor package is provided including a first semiconductor chip stack and a second semiconductor chip stack that are adjacent to each other. The first semiconductor chip stack includes a plurality of first semiconductor chips and a plurality of first adhesive layers. The second semiconductor chip stack includes a plurality of second semiconductor chips and a plurality of second adhesive layers. Each of the first semiconductor chips includes a first cell region and a first scribe lane that surrounds the first cell region. Each of the second semiconductor chips includes a second cell region and a second scribe lane that surrounds the second cell region. An area of the first scribe lane is greater than an area of the second scribe lane. The plurality of first adhesive layers and the plurality of second adhesive layers have the same coefficient of thermal expansion.
    Type: Application
    Filed: May 18, 2020
    Publication date: March 25, 2021
    Inventors: JUNYEONG HEO, JAE-EUN LEE, YEONGKWON KO, DONGHOON WON
  • Publication number: 20210050264
    Abstract: There is provided a method of dicing a semiconductor wafer, which includes providing a semiconductor substrate having a plurality of integrated circuit regions on an active surface of the semiconductor substrate, a dicing regions provided between adjacent integrated circuit regions of the plurality of integrated circuit regions, and a metal shield layer provided on the active surface across at least a portion of the adjacent integrated circuit regions and the dicing region, forming a modified layer by irradiating laser to an inside of the semiconductor substrate along the dicing region, propagating a crack from the modified layer in a direction perpendicular to a major-axial direction of the metal shield layer by polishing an inactive surface opposing the active surface of the semiconductor substrate and forming semiconductor chips by separating the adjacent integrated circuit regions, respectively, based on the crack propagating from the modified layer.
    Type: Application
    Filed: May 11, 2020
    Publication date: February 18, 2021
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Donghoon WON, Jaeeun Lee, Yeongkwon Ko, Junyeong Heo
  • Patent number: 9875992
    Abstract: An embodiment includes a semiconductor package comprising: a substrate; a first semiconductor chip mounted on the substrate; a second semiconductor chip mounted on a top surface of the first semiconductor chip; a connecting bump disposed between the first and second semiconductor chips to electrically connect the second semiconductor chip to the first semiconductor chip; and a first heat dissipation part disposed on the top surface of the first semiconductor chip between the first and second semiconductor chips and spaced apart from a bottom surface of the second semiconductor chip.
    Type: Grant
    Filed: August 9, 2015
    Date of Patent: January 23, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junyeong Heo, Chajea Jo, Taeje Cho
  • Publication number: 20160079208
    Abstract: An embodiment includes a semiconductor package comprising: a substrate; a first semiconductor chip mounted on the substrate; a second semiconductor chip mounted on a top surface of the first semiconductor chip; a connecting bump disposed between the first and second semiconductor chips to electrically connect the second semiconductor chip to the first semiconductor chip; and a first heat dissipation part disposed on the top surface of the first semiconductor chip between the first and second semiconductor chips and spaced apart from a bottom surface of the second semiconductor chip.
    Type: Application
    Filed: August 9, 2015
    Publication date: March 17, 2016
    Inventors: Junyeong HEO, CHAJEA JO, Taeje CHO