Abstract: A method for extending life expectancy of a volatile memory device includes performing a life test corresponding to memory cells included in the volatile memory device, determining whether the memory cells have a normal life state or a shrink-life state indicating a life expectancy that is reduced relative to the normal life state based on a result of the life test, and decreasing a wordline voltage, which is applied to a wordline connected to the memory cells, to a first voltage that is less than a second voltage that is applied to the wordline in the normal life state during a read operation or a write operation responsive to determining that the memory cells have the shrink-life state.

Abstract: The memory device includes a clock receiver receiving an external clock signal, a transmitter receiving first to Nth data in parallel and sequentially outputting the first to Nth data based on first to Nth clock signals including different phases, and a QEC circuit correcting a skew between the first to Nth clock signals, wherein the external clock signal includes a same frequency as the first to Nth clock signals, and the QEC circuit selectively receives the first clock signal among the first to Nth clock signals, generates the second clock signal including a phase different from a phase of the first clock signal based on a delay operation with respect to the first clock signal, and corrects the skew between the first to Nth clock signals by performing a phase comparison between the first to Nth clock signals generated based on the first and second clock signals.

Abstract: A display panel including a first panel region (FPR) including (n?1)-th and n-th pixel rows ((n?1)PR and nPR), and a second panel region (SPR) dividing the nPR to propagate an optical signal. The display panel includes a circuit element layer (CEL) and a display element layer (DEL). The CEL includes a signal line (SL), a pixel driving circuit (PDC), and first to third regions. The SL and the PDC are in the first region. The second region (SR) corresponds to the SPR. The SL and the PDC are not in the SR. The third region (TR) corresponds to the SPR and is along a periphery of the SR. The SL is in the TR, and includes an (n?1)-th scan line ((n?1)SL) connected to the (n?1)PR, an n-th reset line (nRL) connected to the nPR, and a first row connection line in the TR and connecting the (n?1)SL and the nRL.

Abstract: A transmitter configured to receive first to N-th data in parallel and sequentially output the first to N-th data in response to first to N-th clock signals having different phases from each other, where N is an integer of at least 2, the transmitter including first to N-th data selectors including a first data selector and a second data selector in correspondence to the first to N-th data, each of the first to N-th data selectors being configured to perform a logical operation on one of the first to N-th data and the first to N-th clock signals and output a plurality of data selection signals, a first pre-driver in correspondence to at least two data selectors among the first to N-th data selectors, the first pre-driver being configured to receive the plurality of data selection signals from the at least two data selectors.

Abstract: Discussed is a cradle for a wireless audio device. The cradle can include a casing including a seating groove for seating the wireless audio device, wherein the casing is able to be opened and closed, a transceiver disposed in the casing, a switch formed in a part of the casing, and an external device interface including an input terminal formed in another part of the casing, wherein in response to a first cable being connected to the input terminal in a wired connection mode, one of the transceiver and the external device interface performs a bi-directional wireless audio transmission for audio signal exchange with the wireless audio device, and wherein in response to a second cable being connected to the input terminal in the wired connection mode, one of the transceiver and the external device interface performs a unidirectional wireless audio transmission for audio transmission to the wireless audio device.

Abstract: A semiconductor device includes a phase splitter configured to output a plurality of clock signals having different phases by using a plurality of external clock signals having different phases, a plurality of code generators configured to receive a pair of selection clock signals determined from the plurality of clock signals and to output a phase code corresponding to a phase difference error between the pair of selection clock signals, and a delay circuit configured to at least partly simultaneously adjust at least two of a rising edge and a falling edge of each of the plurality of external clock signals with reference to the phase code during a lock time.

Abstract: A method for calibrating an imaging device comprising a photon counting detector (PCD), the method comprising: providing (i) an X-ray source configured to emit an X-ray beam, (ii) a first detector array configured to be in alignment with the X-ray beam, wherein the first detector array comprises a plurality of energy integrating detectors (EID) for detecting the X-ray beam emitted by the X-ray source, and (iii) a second detector array configured to be in alignment with the X-ray beam, wherein the second detector array comprises a plurality of photo counting detectors (PCD) for detecting the X-ray beam emitted by the X-ray source; detecting an X-ray beam passed through an object to be scanned with the plurality of energy integrating detectors (EID); recording the X-ray beam passed through the object to be scanned and detected by the plurality of energy integrating detectors (EID) as a first data set; detecting an X-ray beam passed through the object to be scanned with the plurality of photo counting detectors

Abstract: An integrated circuit device includes: a semiconductor on insulator (SOI) substrate layer including a base substrate layer, an insulating substrate layer, and a cover substrate layer; a semiconductor substrate layer; a plurality of first fin-type active areas and a plurality of second fin-type active areas each defined by a plurality of trenches, and extending in a first horizontal direction, in above the SOI substrate layer and the semiconductor substrate layer, respectively; a plurality of nanosheet stacked structures comprising nanosheets extending in parallel with each other and spaced apart from upper surfaces of the plurality of first fin-type active areas and the plurality of second fin-type active areas; a plurality of first source/drain regions extending into the SOI substrate layer; and a plurality of second source/drain regions extending into the semiconductor substrate layer. Lower surfaces of the first and second source/drain regions may not be coplanar with each other.

Abstract: According to various embodiments, an electronic device may include a communication circuit operably coupled with an external electronic device and at least one processor, wherein the at least one processor may be configured to determine one or more target-wake-time (TWT) parameters of at least one TWT service period based on at least one of the amount of data transmitted to the external electronic device, an amount of data received from the external electronic device, or a bandwidth, wherein at least one data frame is transmitted or received between the electronic device and the external electronic device during the at least one TWT service period; identify quality of service (QoS) for the at least one data frame transmitted or received during the at least one TWT service period; change at least one TWT parameter among the one or more TWT parameters based on the identified QoS; and control the communication circuit to transmit or receive at least one next data frame during the a next TWT service period based

Abstract: A semiconductor package includes a substrate including a first region, a second region in contact with the first region with the first and second regions stacked in a first direction, and a third region extending from the first and second regions in a second direction, perpendicular to the first direction, to connect the first and second regions to each other in bent form, a first semiconductor chip on a first side opposite to a second side of the first region in contact with the second region, a second semiconductor chip on a first side opposite to a second side of the second region in contact with the first region, a first molding member on the first region and covering at least a portion of the first semiconductor chip, and a second molding member on the second region and covering at least a portion of the second semiconductor chip.

Abstract: A transmitter circuit that receives parallel signals and outputs a serial signal in response to the parallel signals may include; a clock generator generating first clock signals having different respective phases, a multiplexer including selection circuits respectively configured to selectively provide at least two of the parallel signals to an output node in response to at least two of the first clock signals, and an output driver generating the serial signal by amplifying a signal at the output node.

Abstract: An electronic device is provided.

Abstract: A method and an apparatus for controlling communication parameters in multiple communication are provided. The apparatus includes a memory and a processor operatively coupled to the memory, wherein the memory includes instructions for allowing the processor to, set a first service period duration and a first wake interval, related to first communication, on the basis of the quality of service of the first communication, set a second service period duration and a second wake interval, related to second communication, on the basis of the quality of service of the second communication when a second communication connection having a frequency overlapping with that of the first communication is detected, determine whether the time difference between the first wake interval and the second wake interval occurs, and change, on the basis of the determination result, the first wake interval and the second wake interval to correspond to each other.

Abstract: Provided is a system-on-chip including a host central processing unit (CPU) and a secure element, wherein the secure element includes a primary device configured to transmit encrypted data, an internal bus configured to transmit the encrypted data, a plurality of secondary devices configured to receive the encrypted data, and a secure CPU configured to manage access keys indicating authorization of the primary device for accessing the plurality of secondary devices, and the internal bus sets a secondary device to which the encrypted data is to be transmitted from among the plurality of secondary devices, based on the access key and transmits the encrypted data to a set secondary device by using an error detection tag.

Abstract: In a method of generating a multi-level signal having one of three or more voltage levels that are different from one another, input data including two or more bits is received. A drive strength of at least one of two or more driving paths is changed based on the two or more bits such that a first transition time, during which an output data signal is transitioned from a first voltage level to a second voltage level, is changed. The output data signal that is the multi-level signal is generated such that the first transition time of the output data signal is changed and a second transition time, during which the output data signal is transitioned from the first voltage level to a third voltage level different from the second voltage level, is maintained.

Abstract: A transmitter circuit includes a clock generator configured to generate a plurality of clock signals having different phases, and a plurality of selection circuits configured to receive a plurality of parallel data signals and output a serial data signal on an output node based on the plurality of clock signals and the received plurality of parallel data signals. Each of the plurality of selection circuits includes a data multiplexer configured to generate a plurality of data selection signals based on the received one of the plurality of parallel data signals and the plurality of clock signals; a control signal generator configured to generate first and second control signals based on the plurality of data selection signals; and an output driver connected to the output node, and configured to precharge the output node based on the first control signal or discharge the output node based on the second control signal.

Abstract: An electronic device is disclosed herein.

Abstract: A delay circuit for a clock signal includes a first signal generator, a first inverting circuit, a second signal generator and a second inverting circuit. The first signal generator is configured to generate a plurality of first switching signals based on a delay code. The first inverting circuit includes a plurality of first inverters that are selectively turned on in response to the plurality of first switching signals, respectively, and is configured to adjust a first delay time for both of a first edge and a second edge of the clock signal. The second signal generator is configured to generate a plurality of second switching signals based on a duty code. The second inverting circuit includes a plurality of second pull-up units and a plurality of second pull-down units, respective ones of the plurality of second pull-up units or respective ones of the plurality of second pull-down units are selectively turned on in response to respective ones of the plurality of second switching signals.

Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.