Patents by Inventor Junyoung Park

Junyoung Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240040635
    Abstract: An electronic device is provided.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 1, 2024
    Inventors: Junsu CHOI, Junyoung PARK, Hyeonu CHOI, Jeongyong MYOUNG, Junghun LEE
  • Publication number: 20240015597
    Abstract: A method and an apparatus for controlling communication parameters in multiple communication are provided. The apparatus includes a memory and a processor operatively coupled to the memory, wherein the memory includes instructions for allowing the processor to, set a first service period duration and a first wake interval, related to first communication, on the basis of the quality of service of the first communication, set a second service period duration and a second wake interval, related to second communication, on the basis of the quality of service of the second communication when a second communication connection having a frequency overlapping with that of the first communication is detected, determine whether the time difference between the first wake interval and the second wake interval occurs, and change, on the basis of the determination result, the first wake interval and the second wake interval to correspond to each other.
    Type: Application
    Filed: September 22, 2023
    Publication date: January 11, 2024
    Inventors: Junsu CHOI, Junyoung PARK, Hyeonu CHOI, Jeongyong MYOUNG, Junghun LEE
  • Publication number: 20240012950
    Abstract: Provided is a system-on-chip including a host central processing unit (CPU) and a secure element, wherein the secure element includes a primary device configured to transmit encrypted data, an internal bus configured to transmit the encrypted data, a plurality of secondary devices configured to receive the encrypted data, and a secure CPU configured to manage access keys indicating authorization of the primary device for accessing the plurality of secondary devices, and the internal bus sets a secondary device to which the encrypted data is to be transmitted from among the plurality of secondary devices, based on the access key and transmits the encrypted data to a set secondary device by using an error detection tag.
    Type: Application
    Filed: July 10, 2023
    Publication date: January 11, 2024
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bogyeong KANG, Kihong KIM, Junyoung PARK, Jinsub PARK, Jaekeun OH, Youngjae JANG
  • Publication number: 20230395133
    Abstract: In a method of generating a multi-level signal having one of three or more voltage levels that are different from one another, input data including two or more bits is received. A drive strength of at least one of two or more driving paths is changed based on the two or more bits such that a first transition time, during which an output data signal is transitioned from a first voltage level to a second voltage level, is changed. The output data signal that is the multi-level signal is generated such that the first transition time of the output data signal is changed and a second transition time, during which the output data signal is transitioned from the first voltage level to a third voltage level different from the second voltage level, is maintained.
    Type: Application
    Filed: August 14, 2023
    Publication date: December 7, 2023
    Inventors: Junyoung PARK, Younghoon SON, Hyunyoon CHO, Youngdon CHOI, Junghwan CHOI
  • Patent number: 11804838
    Abstract: A transmitter circuit includes a clock generator configured to generate a plurality of clock signals having different phases, and a plurality of selection circuits configured to receive a plurality of parallel data signals and output a serial data signal on an output node based on the plurality of clock signals and the received plurality of parallel data signals. Each of the plurality of selection circuits includes a data multiplexer configured to generate a plurality of data selection signals based on the received one of the plurality of parallel data signals and the plurality of clock signals; a control signal generator configured to generate first and second control signals based on the plurality of data selection signals; and an output driver connected to the output node, and configured to precharge the output node based on the first control signal or discharge the output node based on the second control signal.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: October 31, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junyoung Park, Joohwan Kim, Jindo Byun, Eunseok Shin, Hyunyoon Cho, Youngdon Choi, Junghwan Choi
  • Patent number: 11800438
    Abstract: An electronic device is disclosed herein.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: October 24, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongmu Choi, Heechan Kim, Junyoung Park, Bokun Choi, Hyunah Oh, Seongyu Cho
  • Patent number: 11791811
    Abstract: A delay circuit for a clock signal includes a first signal generator, a first inverting circuit, a second signal generator and a second inverting circuit. The first signal generator is configured to generate a plurality of first switching signals based on a delay code. The first inverting circuit includes a plurality of first inverters that are selectively turned on in response to the plurality of first switching signals, respectively, and is configured to adjust a first delay time for both of a first edge and a second edge of the clock signal. The second signal generator is configured to generate a plurality of second switching signals based on a duty code. The second inverting circuit includes a plurality of second pull-up units and a plurality of second pull-down units, respective ones of the plurality of second pull-up units or respective ones of the plurality of second pull-down units are selectively turned on in response to respective ones of the plurality of second switching signals.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: October 17, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunsub Rie, Eunseok Shin, Youngdon Choi, Junyoung Park, Hyunyoon Cho, Junghwan Choi
  • Publication number: 20230280782
    Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.
    Type: Application
    Filed: May 11, 2023
    Publication date: September 7, 2023
    Inventors: Junyoung PARK, YOUNG-HOON SON, HYUN-YOON CHO, YOUNGDON CHOI, JUNGHWAN CHOI
  • Publication number: 20230260923
    Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.
    Type: Application
    Filed: April 26, 2023
    Publication date: August 17, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ju-Il CHOI, Gyuho Kang, Un-Byoung Kang, Byeongchan Kim, Junyoung Park, Jongho Lee, Hyunsu Hwang
  • Publication number: 20230253018
    Abstract: A method of generating a multi-level signal having one of three or more voltage levels that are different from each other, the method including: performing a first voltage setting operation in which first and second voltage intervals are adjusted to be different from each other, wherein the first voltage interval represents a difference between a first pair of adjacent voltage levels and the second voltage interval represents a difference between a second pair of adjacent voltage levels; performing a second voltage setting operation in which a voltage swing width is adjusted, the voltage swing width representing a difference between a lowest and a highest voltage level among the three or more voltage levels; and generating an output data signal that is the multi-level signal based on input data including two or more bits, a result of the first voltage setting operation and a result of the second voltage setting operation.
    Type: Application
    Filed: April 14, 2023
    Publication date: August 10, 2023
    Inventors: Junyoung Park, Jaewoo Park, Younghoon Son, Youngdon Choi, Junghwan Choi
  • Patent number: 11708770
    Abstract: A casing component is configured to form part of a flow path in a turbine. The casing component includes a base made of nodular cast iron, and a repaired region in the base. The repaired region includes a butter layer applied on the base and a fill layer applied on the butter layer.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: July 25, 2023
    Assignee: General Electric Company
    Inventors: Krzysztof Dynak, Sharon Trombly Swede, Junyoung Park, Marek Miekus, Tomasz Michal Szewczyk, Robert Lebkowski
  • Patent number: 11687114
    Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: June 27, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junyoung Park, Young-Hoon Son, Hyun-Yoon Cho, Youngdon Choi, Junghwan Choi
  • Patent number: 11682630
    Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: June 20, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Il Choi, Gyuho Kang, Un-Byoung Kang, Byeongchan Kim, Junyoung Park, Jongho Lee, Hyunsu Hwang
  • Patent number: 11649472
    Abstract: The disclosure provides methods using mixed substrate cofeeding for bioproduct synthesis, which enables faster, more efficient, and higher yield carbon conversion in various organisms.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 16, 2023
    Assignee: Massachusetts Institute of Technology
    Inventors: Junyoung Park, Nian Liu, Gregory Stephanopoulos
  • Patent number: 11651799
    Abstract: A method of generating a multi-level signal having one of three or more voltage levels that are different from each other, the method including: performing a first voltage setting operation in which first and second voltage intervals are adjusted to be different from each other, wherein the first voltage interval represents a difference between a first pair of adjacent voltage levels and the second voltage interval represents a difference between a second pair of adjacent voltage levels; performing a second voltage setting operation in which a voltage swing width is adjusted, the voltage swing width representing a difference between a lowest and a highest voltage level among the three or more voltage levels; and generating an output data signal that is the multi-level signal based on input data including two or more bits, a result of the first voltage setting operation and a result of the second voltage setting operation.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: May 16, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junyoung Park, Jaewoo Park, Younghoon Son, Youngdon Choi, Junghwan Choi
  • Publication number: 20230110301
    Abstract: A delay circuit for a clock signal includes a first signal generator, a first inverting circuit, a second signal generator and a second inverting circuit. The first signal generator is configured to generate a plurality of first switching signals based on a delay code. The first inverting circuit includes a plurality of first inverters that are selectively turned on in response to the plurality of first switching signals, respectively, and is configured to adjust a first delay time for both of a first edge and a second edge of the clock signal. The second signal generator is configured to generate a plurality of second switching signals based on a duty code. The second inverting circuit includes a plurality of second pull-up units and a plurality of second pull-down units, respective ones of the plurality of second pull-up units or respective ones of the plurality of second pull-down units are selectively turned on in response to respective ones of the plurality of second switching signals.
    Type: Application
    Filed: June 14, 2022
    Publication date: April 13, 2023
    Inventors: Hyunsub Rie, Eunseok Shin, Youngdon Choi, Junyoung Park, Hyunyoon Cho, Junghwan Choi
  • Publication number: 20230007379
    Abstract: An electronic device is disclosed. The electronic device according to the present disclosure includes a body, a neck formed at one side of the body, and a head formed on the neck, wherein the head comprises: a circular part connected to the neck; a protrusion part protruding from one side of the circular part and having a curvature that is greater than a curvature of the circular part; a speaker hole formed at at least one of the circular part and the protrusion part; and a band part formed at the periphery of the speaker hole, and the thickness of the band part may be greater than the thickness of the circular part or the protrusion part around the band part.
    Type: Application
    Filed: January 30, 2020
    Publication date: January 5, 2023
    Applicant: LG ELECTRONICS INC.
    Inventors: Youngjin AHN, Kyoungsu NAM, Donghan KIM, Sungwon KIM, Junyoung PARK, Obyoung KANG, Juchul YUN
  • Publication number: 20220399316
    Abstract: Disclosed is a semiconductor package comprising an interposer substrate having first and second surfaces opposite each other and including a wiring layer adjacent to the first surface, a semiconductor chip on the first surface of the interposer substrate, a passivation layer on the first surface of the interposer substrate and covering the semiconductor chip, and redistribution patterns in the passivation layer and connected to the semiconductor chip. The semiconductor chip has third and fourth surfaces opposite to each other. The third surface of the semiconductor chip faces the first surface of the interposer substrate. The redistribution patterns are connected to the fourth surface of the semiconductor chip. The semiconductor chip includes chip pads adjacent to the third surface and chip through electrodes connected to the chip pads. Each of the chip pads is directly bonded to a corresponding one of wiring patterns in the wiring layer.
    Type: Application
    Filed: February 22, 2022
    Publication date: December 15, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ju-Il CHOI, Gyuho KANG, Heewon KIM, Sechul PARK, Jongho PARK, Junyoung PARK
  • Publication number: 20220385287
    Abstract: A transmitter circuit includes a clock generator configured to generate a plurality of clock signals having different phases, and a plurality of selection circuits configured to receive a plurality of parallel data signals and output a serial data signal on an output node based on the plurality of clock signals and the received plurality of parallel data signals. Each of the plurality of selection circuits includes a data multiplexer configured to generate a plurality of data selection signals based on the received one of the plurality of parallel data signals and the plurality of clock signals; a control signal generator configured to generate first and second control signals based on the plurality of data selection signals; and an output driver connected to the output node, and configured to precharge the output node based on the first control signal or discharge the output node based on the second control signal.
    Type: Application
    Filed: May 23, 2022
    Publication date: December 1, 2022
    Inventors: Junyoung PARK, Joohwan KIM, Jindo BYUN, Eunseok SHIN, Hyunyoon CHO, Youngdon CHOI, Junghwan CHOI
  • Publication number: 20220382317
    Abstract: A transmitter circuit that receives parallel signals and outputs a serial signal in response to the parallel signals may include; a clock generator generating first clock signals having different respective phases, a multiplexer including selection circuits respectively configured to selectively provide at least two of the parallel signals to an output node in response to at least two of the first clock signals, and an output driver generating the serial signal by amplifying a signal at the output node.
    Type: Application
    Filed: May 5, 2022
    Publication date: December 1, 2022
    Inventors: JUNYOUNG PARK, JOOHWAN KIM, JINDO BYUN, EUNSEOK SHIN, HYUNYOON CHO, YOUNGDON CHOI, JUNGHWAN CHOI