Abstract: In a method of generating a multi-level signal having one of three or more voltage levels that are different from one another, input data including two or more bits is received. A drive strength of at least one of two or more driving paths is changed based on the two or more bits such that a first transition time, during which an output data signal is transitioned from a first voltage level to a second voltage level, is changed. The output data signal that is the multi-level signal is generated such that the first transition time of the output data signal is changed and a second transition time, during which the output data signal is transitioned from the first voltage level to a third voltage level different from the second voltage level, is maintained.

Abstract: A transmitter circuit includes a clock generator configured to generate a plurality of clock signals having different phases, and a plurality of selection circuits configured to receive a plurality of parallel data signals and output a serial data signal on an output node based on the plurality of clock signals and the received plurality of parallel data signals. Each of the plurality of selection circuits includes a data multiplexer configured to generate a plurality of data selection signals based on the received one of the plurality of parallel data signals and the plurality of clock signals; a control signal generator configured to generate first and second control signals based on the plurality of data selection signals; and an output driver connected to the output node, and configured to precharge the output node based on the first control signal or discharge the output node based on the second control signal.

Abstract: An electronic device is disclosed herein.

Abstract: A delay circuit for a clock signal includes a first signal generator, a first inverting circuit, a second signal generator and a second inverting circuit. The first signal generator is configured to generate a plurality of first switching signals based on a delay code. The first inverting circuit includes a plurality of first inverters that are selectively turned on in response to the plurality of first switching signals, respectively, and is configured to adjust a first delay time for both of a first edge and a second edge of the clock signal. The second signal generator is configured to generate a plurality of second switching signals based on a duty code. The second inverting circuit includes a plurality of second pull-up units and a plurality of second pull-down units, respective ones of the plurality of second pull-up units or respective ones of the plurality of second pull-down units are selectively turned on in response to respective ones of the plurality of second switching signals.

Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

Abstract: A method of generating a multi-level signal having one of three or more voltage levels that are different from each other, the method including: performing a first voltage setting operation in which first and second voltage intervals are adjusted to be different from each other, wherein the first voltage interval represents a difference between a first pair of adjacent voltage levels and the second voltage interval represents a difference between a second pair of adjacent voltage levels; performing a second voltage setting operation in which a voltage swing width is adjusted, the voltage swing width representing a difference between a lowest and a highest voltage level among the three or more voltage levels; and generating an output data signal that is the multi-level signal based on input data including two or more bits, a result of the first voltage setting operation and a result of the second voltage setting operation.

Abstract: A casing component is configured to form part of a flow path in a turbine. The casing component includes a base made of nodular cast iron, and a repaired region in the base. The repaired region includes a butter layer applied on the base and a fill layer applied on the butter layer.

Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

Abstract: The disclosure provides methods using mixed substrate cofeeding for bioproduct synthesis, which enables faster, more efficient, and higher yield carbon conversion in various organisms.

Abstract: A method of generating a multi-level signal having one of three or more voltage levels that are different from each other, the method including: performing a first voltage setting operation in which first and second voltage intervals are adjusted to be different from each other, wherein the first voltage interval represents a difference between a first pair of adjacent voltage levels and the second voltage interval represents a difference between a second pair of adjacent voltage levels; performing a second voltage setting operation in which a voltage swing width is adjusted, the voltage swing width representing a difference between a lowest and a highest voltage level among the three or more voltage levels; and generating an output data signal that is the multi-level signal based on input data including two or more bits, a result of the first voltage setting operation and a result of the second voltage setting operation.

Abstract: A delay circuit for a clock signal includes a first signal generator, a first inverting circuit, a second signal generator and a second inverting circuit. The first signal generator is configured to generate a plurality of first switching signals based on a delay code. The first inverting circuit includes a plurality of first inverters that are selectively turned on in response to the plurality of first switching signals, respectively, and is configured to adjust a first delay time for both of a first edge and a second edge of the clock signal. The second signal generator is configured to generate a plurality of second switching signals based on a duty code. The second inverting circuit includes a plurality of second pull-up units and a plurality of second pull-down units, respective ones of the plurality of second pull-up units or respective ones of the plurality of second pull-down units are selectively turned on in response to respective ones of the plurality of second switching signals.

Abstract: An electronic device is disclosed. The electronic device according to the present disclosure includes a body, a neck formed at one side of the body, and a head formed on the neck, wherein the head comprises: a circular part connected to the neck; a protrusion part protruding from one side of the circular part and having a curvature that is greater than a curvature of the circular part; a speaker hole formed at at least one of the circular part and the protrusion part; and a band part formed at the periphery of the speaker hole, and the thickness of the band part may be greater than the thickness of the circular part or the protrusion part around the band part.

Abstract: Disclosed is a semiconductor package comprising an interposer substrate having first and second surfaces opposite each other and including a wiring layer adjacent to the first surface, a semiconductor chip on the first surface of the interposer substrate, a passivation layer on the first surface of the interposer substrate and covering the semiconductor chip, and redistribution patterns in the passivation layer and connected to the semiconductor chip. The semiconductor chip has third and fourth surfaces opposite to each other. The third surface of the semiconductor chip faces the first surface of the interposer substrate. The redistribution patterns are connected to the fourth surface of the semiconductor chip. The semiconductor chip includes chip pads adjacent to the third surface and chip through electrodes connected to the chip pads. Each of the chip pads is directly bonded to a corresponding one of wiring patterns in the wiring layer.

Abstract: A transmitter circuit includes a clock generator configured to generate a plurality of clock signals having different phases, and a plurality of selection circuits configured to receive a plurality of parallel data signals and output a serial data signal on an output node based on the plurality of clock signals and the received plurality of parallel data signals. Each of the plurality of selection circuits includes a data multiplexer configured to generate a plurality of data selection signals based on the received one of the plurality of parallel data signals and the plurality of clock signals; a control signal generator configured to generate first and second control signals based on the plurality of data selection signals; and an output driver connected to the output node, and configured to precharge the output node based on the first control signal or discharge the output node based on the second control signal.

Abstract: A transmitter circuit that receives parallel signals and outputs a serial signal in response to the parallel signals may include; a clock generator generating first clock signals having different respective phases, a multiplexer including selection circuits respectively configured to selectively provide at least two of the parallel signals to an output node in response to at least two of the first clock signals, and an output driver generating the serial signal by amplifying a signal at the output node.

Abstract: Systems and methods for altering microstructures of materials are disclosed. The system may include at least one computing device in communication with a heating device and an electromagnetic device. The computing device(s) may be configured to alter a microstructure of a material forming a component by performing processes including heating the component using the heating device to a predetermined temperature. The predetermined temperature may be below a first phase-transformation temperature based on the material forming the component, and a second phase-transformation temperature based on the material forming the component, where the second phase-transformation temperature greater than the first phase-transformation temperature. The computing device(s) may also perform processes including intermittently magnetizing the heated component using the electromagnetic device for a predetermined number of cycles, and cooling the component after intermittently magnetizing the heated component.

Abstract: An amplifying device includes a main amplifier; a first feedback circuit coupled between an input terminal of the main amplifier and an output terminal of the main amplifier; an input coupling circuit coupled between the input terminal of the main amplifier and a first node; and an amplifying feedback circuit coupled between the output terminal of the main amplifier and the first node, wherein the first feedback circuit and the amplifying feedback circuit are negative feedback circuits.

Abstract: A casing component is configured to form part of a flow path in a turbine. The casing component includes a base made of nodular cast iron, and a repaired region in the base. The repaired region includes a butter layer applied on the base and a fill layer applied on the butter layer.