Patents by Inventor Jun Young Yang

Jun Young Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250314064
    Abstract: The present invention relates to a method for changing the envelope structure of a building to improve functions or facilitate modifying same of a building in accordance with user requests without any reduction to the usable interior space of the building, the method comprising the steps of: a) separating, from an exterior structure, the target exterior enclosure the function of which is to be changed; b) sliding and pulling out the target exterior enclosure, like a drawer, along a guide frame to the outside of the exterior structure; (c) removing a cartridge inside the target exterior enclosure and inserting a cartridge having a new function; and (d) inserting the target exterior enclosure back into the exterior structure by sliding the target exterior enclosure, like a drawer, along the guide panel.
    Type: Application
    Filed: January 30, 2024
    Publication date: October 9, 2025
    Applicant: SAMOO ARCHITECTS&ENGINEERS CO.,LTD
    Inventors: Chang Kyu SOHN, Dong Hoon KIM, Ju Byung LEE, Shin Jae LEE, Ha Won YOON, Dae Soon KIM, Jun Young YANG, GUEN IL HUH, Jun Yub KIM, Sang Eun HAN
  • Publication number: 20250314126
    Abstract: The present invention relates to a louver apparatus with independent top and bottom, the louver allowing being opened and closed from the top or bottom independently. The louver apparatus comprises: a rail means comprising an upper rail and a lower rail; a turning means installed in accommodating spaces of the upper and lower rails so as to be operated independently; and a louver means positioned between the upper rail and lower rail to rotate the slats according to the operation of the turning means.
    Type: Application
    Filed: January 30, 2024
    Publication date: October 9, 2025
    Applicant: SAMOO ARCHITECTS&ENGINEERS CO.,LTD
    Inventors: Chang Kyu SOHN, Dong Hoon KIM, Ju Byung LEE, Shin Jae LEE, Ha Won YOON, Dae Soon KIM, Jun Young YANG, GUEN IL HUH, Jun Yub KIM, Sang Eun HAN
  • Patent number: 8625814
    Abstract: An earphone antenna of a portable terminal having enhanced reception sensitivity even when a wearing state of the earphone of the mobile terminal is changed is provided. The earphone antenna includes a plurality of voice signal lines, an insulating sheath configured to cover an outer surface of the plurality of the voice signal lines, a receptacle configured to connect to a first end of each of the plurality of the voice signal lines, and a ground and antenna line including a first antenna line configured to wind around an outer surface of the insulating sheath at a first interval in a spiral form, the first antenna line having a first thickness, wherein the ground and antenna line includes a second antenna line configured to wind around an outer surface of the receptacle at a second interval in the spiral form, the second antenna line having a second thickness that is greater than the first thickness and the second interval being different from the first interval.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: January 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Young Yang, Min Cho, Byoung Hee Lee
  • Patent number: 8154111
    Abstract: A semiconductor package that can fit semiconductor chips of various sizes without having to change the footprint of the carrier package. One aspect of the semiconductor package comprises a leadframe, a semiconductor chip attached to the leadframe, electrical connectors electrically connecting the semiconductor chip to the leadframe, and a sealing material. The leadframe has a plurality of leads, with each one of the plurality of leads having an upper side, a lower exposed side, and a laterally exposed side. The upper side of each one of the plurality of leads defines a generally co-planar surface. Further, after sealing material encapsulates the components of the semiconductor package in a spatial relationship, the lower exposed side and the lateral exposed side of the plurality of leads are exposed to the outside surface of the semiconductor package.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: April 10, 2012
    Assignee: Amkor Technology, Inc.
    Inventors: Sean Timothy Crowley, Angel Orabuena Alvarez, Jun Young Yang
  • Publication number: 20110274285
    Abstract: An earphone antenna of a portable terminal having enhanced reception sensitivity even when a wearing state of the earphone of the mobile terminal is changed is provided. The earphone antenna includes a plurality of voice signal lines, an insulating sheath configured to cover an outer surface of the plurality of the voice signal lines, a receptacle configured to connect to a first end of each of the plurality of the voice signal lines, and a ground and antenna line including a first antenna line configured to wind around an outer surface of the insulating sheath at a first interval in a spiral form, the first antenna line having a first thickness, wherein the ground and antenna line includes a second antenna line configured to wind around an outer surface of the receptacle at a second interval in the spiral form, the second antenna line having a second thickness that is greater than the first thickness and the second interval being different from the first interval.
    Type: Application
    Filed: May 3, 2011
    Publication date: November 10, 2011
    Applicant: SAMSUNG ELECTRONICS CO. LTD.
    Inventors: Jun Young YANG, Min CHO, Byoung Hee LEE
  • Patent number: 7833837
    Abstract: A chip scale package includes a patterned circuit layer attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive layer such that contact pads on a lower surface of the patterned circuit layer are electrically coupled to corresponding bonding pads on the semiconductor chip. The patterned circuit layer has a plurality of openings formed therein at locations corresponding to the contact pads such that each of the contact pads has a portion exposed from an upper surface of the patterned circuit layer through the corresponding opening. A plurality of metal bumps are respectively disposed in the openings and mounted to the exposed portions of the contact pads for making external electrical connection. The present invention further provides a method for manufacturing the chip scale package at the wafer-level.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: November 16, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Jun Young Yang, You Ock Joo, Dong Pil Jung
  • Patent number: 7700411
    Abstract: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The present invention further provides methods for manufacturing the semiconductor device package.
    Type: Grant
    Filed: September 7, 2007
    Date of Patent: April 20, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Jun Young Yang, You Ock Joo, Dong Pil Jung
  • Patent number: 7656047
    Abstract: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The electromagnetic interference shielding layer is a plated metal layer in contact with the package body, and the plated metal layer is connected to a ground trace extending on the upper surface of the substrate.
    Type: Grant
    Filed: September 7, 2007
    Date of Patent: February 2, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Jun Young Yang, You Ock Joo, You Pil Jung
  • Patent number: 7633170
    Abstract: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The present invention further provides methods for manufacturing the semiconductor device package.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: December 15, 2009
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Jun Young Yang, You Ock Joo, Dong Pil Jung
  • Publication number: 20080174013
    Abstract: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The present invention further provides methods for manufacturing the semiconductor device package.
    Type: Application
    Filed: February 27, 2008
    Publication date: July 24, 2008
    Inventors: Jun Young YANG, You Ock JOO, Dong Pil JUNG
  • Publication number: 20080042301
    Abstract: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The electromagnetic interference shielding layer is a plated metal layer in contact with the package body, and the plated metal layer is connected to a ground trace extending on the upper surface of the substrate.
    Type: Application
    Filed: September 7, 2007
    Publication date: February 21, 2008
    Applicants: ENGINEERING, INC.
    Inventors: Jun Young Yang, You Joo, You Pil Jung
  • Patent number: 7166917
    Abstract: A semiconductor package includes a semiconductor device and a passive component mounted and electrically coupled to a substrate. The passive component is disposed within a cavity portion formed on an upper surface of the substrate and the semiconductor device is disposed across the cavity portion of the substrate above the passive component.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: January 23, 2007
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventors: Jun Young Yang, You Ock Joo, Dong Pil Jung
  • Patent number: 7146106
    Abstract: An optic semiconductor package includes a main board of a substantially planar plate shape. The main board includes an aperture therethrough and a plurality of board metal patterns formed at the periphery of the aperture. A package portion is coupled to the main board. The package portion includes a base, a laser diode and a photo detector electrically coupled to the board metal patterns of the main board and bonded to the base. An optical fiber is inserted into the aperture of the main board and disposed adjacent the package portion. The position and tilt of the optical fiber may be adjusted to achieve optimum optical coupling between the optical fiber and the laser diode and the optical fiber and the photo detector. The optical fiber is stably attached to the main board by an adhesive.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: December 5, 2006
    Assignee: Amkor Technology, Inc.
    Inventors: Jun Young Yang, Sang Ho Lee, Chul Woo Park
  • Publication number: 20060145339
    Abstract: A semiconductor package includes a semiconductor device and a passive component mounted and electrically coupled to a substrate. The passive component is disposed within a cavity portion formed on an upper surface of the substrate and the semiconductor device is disposed across the cavity portion of the substrate above the passive component.
    Type: Application
    Filed: January 5, 2005
    Publication date: July 6, 2006
    Inventors: Jun Young Yang, You Ock Joo, Dong Pil Jung
  • Patent number: 7045396
    Abstract: Leadframe-type semiconductor packages that allow the semiconductor packages to be stacked on top of each other. One aspect of the semiconductor package includes a leadframe, a plurality of electrical connectors, a semiconductor chip, and a sealing material for encapsulating the above components. The leadframe has a plurality of leads, with each one of the plurality of leads running from the top of the semiconductor package to the bottom of the semiconductor package. Each one of the plurality of leads has a top portion protruding from the top surface of the semiconductor package and a bottom portion protruding from the top surface of the semiconductor package and a bottom portion protruding from the bottom surface of the semiconductor package. The leads allow for electrical connection of a second semiconductor package placed on top of the first semiconductor package. Further, the protruding parts of the leads form a space between the stacked semiconductor packages for improved heat dissipation.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: May 16, 2006
    Assignee: Amkor Technology, Inc.
    Inventors: Sean Timothy Crowley, Angel Orabuena Alvarez, Jun Young Yang
  • Publication number: 20060063357
    Abstract: A singulation method used in a process for making a plurality of image sensor packages is disclosed. Firstly, a semi-finished product including a plurality of package structures formed on a substrate is placed on a support having a plurality of cavities for receiving the package structures. Then, the semi-finished product is sawed into separate image sensor packages. During the sawing step, the air pressure in the cavities is decreased to create suction within the cavities such that the support abuts against at least a portion of the housing of each package structure with a gap between the transparent component and the support whereby the package structures are positioned precisely and clamped in place with the support during the sawing step.
    Type: Application
    Filed: September 20, 2004
    Publication date: March 23, 2006
    Inventors: Jun Young Yang, In Ho Kim
  • Patent number: 6995448
    Abstract: A semiconductor package including passive elements and a method of manufacturing provide reduced package size, improved performance and higher process yield by mounting the passive elements beneath the semiconductor die on the substrate. The semiconductor die may be mounted above the passive elements by mechanically bonding the semiconductor die to the passive elements, mounting the passive elements within a recess in the substrate or mounting the semiconductor using an adhesive retaining wall on the substrate that protrudes above and extends around the passive elements. The recess may include an aperture through the substrate to vent the package to the outside environment or may comprise an aperture through the substrate and larger than the semiconductor die, permitting the encapsulation to entirely fill the aperture, covering the die and the passive elements to secure them mechanically within the package.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: February 7, 2006
    Assignee: Amkor Technology, Inc.
    Inventors: Sang Ho Lee, Jun Young Yang, Seon Goo Lee, Jong Hae Hyun, Choon Heung Lee
  • Patent number: 6879034
    Abstract: A semiconductor package comprising a low temperature co-fired ceramic substrate defining opposed top and bottom surfaces. The substrate comprises at least two stacked ceramic layers and electrically conductive patterns which extend between the layers and along the top surface of the substrate. Mounted to the top surface of the substrate and electrically connected to the conductive patterns is at least one semiconductor die. A plurality of leads extend at least partially about the substrate in spaced relation thereto. Each of the leads defines opposed top and bottom surfaces, the semiconductor die being electrically connected to at least one of the leads. A package body at least partially encapsulates the substrate, the semiconductor die and the leads such that at least a portion of the bottom surface of each of the leads is exposed in the package body.
    Type: Grant
    Filed: May 1, 2003
    Date of Patent: April 12, 2005
    Assignee: Amkor Technology, Inc.
    Inventors: Jun Young Yang, Sun Goo Lee, Choon Heung Lee
  • Patent number: 6730544
    Abstract: A stackable semiconductor package having a lead frame, a plurality of electrical paths, and a sealing material. The leadframe has a plurality of leads, each one of the plurality of leads having a top portion exposed to a top surface of the semiconductor package and a bottom portion resting flush with a bottom surface of the semiconductor package. In this manner, the leads extending from the top surface to the bottom surface of the semiconductor package provide an electrical path for connecting and electrically powering a second semiconductor package stacked on top of a first bottom semiconductor package.
    Type: Grant
    Filed: October 13, 2000
    Date of Patent: May 4, 2004
    Assignee: Amkor Technology, Inc.
    Inventor: Jun Young Yang
  • Publication number: 20040056338
    Abstract: A semiconductor package that can fit semiconductor chips of various sizes without having to change the footprint of the carrier package. One aspect of the semiconductor package comprises a leadframe, a semiconductor chip attached to the leadframe, electrical connectors electrically connecting the semiconductor to the leadframe, and a sealing material. The leadframe has a plurality of leads, with each one of the plurality of leads having an upper side, a lower exposed side, and a laterally exposed side. The upper side of each one of the plurality of leads define a generally co-planar surface. Further, after sealing material encapsulates the components of the semiconductor package in a spacial relationship, the lower exposed side and the lateral exposed side of the plurality of leads are exposed to the outside surface of the semiconductor package.
    Type: Application
    Filed: September 15, 2003
    Publication date: March 25, 2004
    Inventors: Sean Timothy Crowley, Angel Orabuena Alvarez, Jun Young Yang