Patents by Inventor Jun Young Yang
Jun Young Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250109480Abstract: The present disclosure provides a low dielectric polymer substrate and a preparation method thereof. More specifically, the present disclosure provides a low dielectric polymer substrate to which metal or ceramic may be deposited with high adhesion without a separate adhesive layer through surface modification of a polymer substrate and a preparation method thereof.Type: ApplicationFiled: December 10, 2021Publication date: April 3, 2025Inventors: Sung-hoon JUNG, Do-geun KIM, Seung-hoon LEE, Joo-young PARK, Eun-yeon BYEON, Jun-yeong YANG
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Patent number: 12261176Abstract: A display device includes: a substrate including a display area and a non-display area; a transistor and a light emitting element, which are disposed on the display area; a pad portion disposed in the non-display area, where the pad portion includes a first metal pattern; and a printed circuit board or a data driver, which is connected with the pad portion. The transistor includes a semiconductor layer disposed on the substrate and a source electrode or a drain electrode which is electrically connected with the semiconductor layer. The source electrode or the drain electrode includes a first layer including a first metal, a second layer including a second metal, and a third layer including the first metal, where the first metal pattern includes the first metal, and is connected with the printed circuit board or the data driver.Type: GrantFiled: December 2, 2021Date of Patent: March 25, 2025Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Kohei Ebisuno, Jin-Suk Lee, Jong Min Lee, Jun Young Kim, Yong Ho Yang
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Patent number: 12260046Abstract: A driving circuit includes: a display driver to generate a horizontal synchronization signal and a vertical synchronization signal according to a first clock signal of a first oscillator; a sensor driver to generate a touch signal according to a second clock signal of a second oscillator; and a determination circuit to detect a cycle of at least one of the horizontal synchronization signal or the vertical synchronization signal according to the second clock signal, and output a detection signal when the cycle is out of a range. The determination circuit is a part of the display driver or the sensor driver.Type: GrantFiled: June 26, 2023Date of Patent: March 25, 2025Assignee: Samsung Display Co., Ltd.Inventors: Jun Young Ko, Tae Hyeon Yang, Han Su Cho, Tae Joon Kim, Hyun Wook Cho, Jae Woo Choi
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Publication number: 20250094773Abstract: A method, of training an anomaly detecting model using a plurality of pieces of graph data, includes: (a) inputting one piece of graph data that has not yet been input, among the plurality of pieces of graph data, to a graph neural network (GNN) AutoEncoder calculating a probability of each edge as input data; (b) calculating a difference value (hereinafter, “edge difference value”) between an edge probability value of reconstructed data output by the GNN AutoEncoder and an edge value of the input data; (c) calculating an average value (hereinafter, “positive edge loss”) of a positive edge and an average value (hereinafter, “negative edge loss”) of a negative edge using the edge difference value, and calculating an edge prediction loss value of the reconstructed data by summing the positive edge loss and the negative edge loss; (d) retraining the GNN AutoEncoder until the edge prediction loss value is minimized.Type: ApplicationFiled: December 2, 2024Publication date: March 20, 2025Applicant: UDMTEK CO., LTD.Inventors: Gi Nam Wang, Jun Pyo Park, Seung Woo Han, Geun Ho Yu, Min Young Jung, Hee Chan Yang, Seung Jong Jin
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Publication number: 20250096407Abstract: Disclosed herein is a battery pack. The battery pack can include a plurality of battery cells, a pack case defining a housing configured to accommodate the battery cells, a first venting path extending across the pack case, and a second venting path extending along at least one peripheral side of the pack case. The first venting path can provide a conduit for a gas generated from any of the battery cells. The second venting path can be in fluid communication with the first venting path and an opening on the pack case such that the gas from the battery cells is configured to travel from the first venting path to the second venting path and to be discharged from the battery pack via the opening.Type: ApplicationFiled: September 9, 2024Publication date: March 20, 2025Applicant: LG Energy Solution, Ltd.Inventors: Yong-Ho Lee, So-Jeong Park, Jong-Min Song, Jun-Young Ahn, Kwang-Keun Oh, In-Hyuk Jung, Jin-Oh Yang
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Patent number: 9236356Abstract: A semiconductor package includes a substrate, a grounding layer, a chip, a package body, and a shielding layer. The substrate includes a lateral surface and a bottom surface. The grounding layer is buried in the substrate and extends horizontally in the substrate. The chip is arranged on the substrate. The package body envelops the chip and includes a lateral surface. The shielding layer covers the lateral surface of the package body and the lateral surface of the substrate, and is electrically connected to the grounding layer, where a bottom surface of the shielding layer is separated from a bottom surface of the substrate.Type: GrantFiled: July 30, 2014Date of Patent: January 12, 2016Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Jun-Young Yang, Sung-Mook Lim
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Publication number: 20150035127Abstract: The present disclosure relates to a semiconductor package and a method of fabricating the same. The semiconductor package includes a substrate, a grounding layer, a chip, a package body, and a shielding layer. The substrate includes a lateral surface and a bottom surface. The grounding layer is buried in the substrate and extends horizontally in the substrate. The chip is arranged on the substrate. The package body envelops the chip and includes a lateral surface. The shielding layer covers the lateral surface of the package body and the lateral surface of the substrate, and is electrically connected to the grounding layer, where a bottom surface of the shielding layer is separated from a bottom surface of the substrate.Type: ApplicationFiled: July 30, 2014Publication date: February 5, 2015Inventors: Jun-Young YANG, Sung-Mook LIM
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Patent number: 8882953Abstract: Disclosed is a method for fabricating a cliché that can prevent formation of a defective thin film pattern, and a method for forming a thin film pattern using the same. The method for fabricating a cliché includes providing a base substrate having first and second regions, forming a first depressed pattern having a first depth and a first width at a first region, and a second depressed pattern having a second width greater than the first width and a depth the same with the first depth at a second region, forming a protective film for exposing the second region and covering the first region, the protective film having adhesivity, forming the second depressed pattern to have a second depth deeper than the first depth of the first depressed pattern at the first region by using the protective film having the adhesivity, and removing the protective film.Type: GrantFiled: October 25, 2010Date of Patent: November 11, 2014Assignee: LG Display Co., Ltd.Inventors: Yun-Ho Kook, Chul-Ho Kim, Sang-Chul Jung, Jeong-Hoon Lee, Nam-Kook Kim, Jun-Young Yang
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Patent number: 8625814Abstract: An earphone antenna of a portable terminal having enhanced reception sensitivity even when a wearing state of the earphone of the mobile terminal is changed is provided. The earphone antenna includes a plurality of voice signal lines, an insulating sheath configured to cover an outer surface of the plurality of the voice signal lines, a receptacle configured to connect to a first end of each of the plurality of the voice signal lines, and a ground and antenna line including a first antenna line configured to wind around an outer surface of the insulating sheath at a first interval in a spiral form, the first antenna line having a first thickness, wherein the ground and antenna line includes a second antenna line configured to wind around an outer surface of the receptacle at a second interval in the spiral form, the second antenna line having a second thickness that is greater than the first thickness and the second interval being different from the first interval.Type: GrantFiled: May 3, 2011Date of Patent: January 7, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jun Young Yang, Min Cho, Byoung Hee Lee
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Patent number: 8154111Abstract: A semiconductor package that can fit semiconductor chips of various sizes without having to change the footprint of the carrier package. One aspect of the semiconductor package comprises a leadframe, a semiconductor chip attached to the leadframe, electrical connectors electrically connecting the semiconductor chip to the leadframe, and a sealing material. The leadframe has a plurality of leads, with each one of the plurality of leads having an upper side, a lower exposed side, and a laterally exposed side. The upper side of each one of the plurality of leads defines a generally co-planar surface. Further, after sealing material encapsulates the components of the semiconductor package in a spatial relationship, the lower exposed side and the lateral exposed side of the plurality of leads are exposed to the outside surface of the semiconductor package.Type: GrantFiled: September 15, 2003Date of Patent: April 10, 2012Assignee: Amkor Technology, Inc.Inventors: Sean Timothy Crowley, Angel Orabuena Alvarez, Jun Young Yang
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Publication number: 20110274285Abstract: An earphone antenna of a portable terminal having enhanced reception sensitivity even when a wearing state of the earphone of the mobile terminal is changed is provided. The earphone antenna includes a plurality of voice signal lines, an insulating sheath configured to cover an outer surface of the plurality of the voice signal lines, a receptacle configured to connect to a first end of each of the plurality of the voice signal lines, and a ground and antenna line including a first antenna line configured to wind around an outer surface of the insulating sheath at a first interval in a spiral form, the first antenna line having a first thickness, wherein the ground and antenna line includes a second antenna line configured to wind around an outer surface of the receptacle at a second interval in the spiral form, the second antenna line having a second thickness that is greater than the first thickness and the second interval being different from the first interval.Type: ApplicationFiled: May 3, 2011Publication date: November 10, 2011Applicant: SAMSUNG ELECTRONICS CO. LTD.Inventors: Jun Young YANG, Min CHO, Byoung Hee LEE
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Publication number: 20110132527Abstract: Disclosed is a method for fabricating a cliché that can prevent formation of a defective thin film pattern, and a method for forming a thin film pattern using the same. The method for fabricating a cliché includes providing a base substrate having first and second regions, forming a first depressed pattern having a first depth and a first width at a first region, and a second depressed pattern having a second width greater than the first width and a depth the same with the first depth at a second region, forming a protective film for exposing the second region and covering the first region, the protective film having adhesivity, forming the second depressed pattern to have a second depth deeper than the first depth of the first depressed pattern at the first region by using the protective film having the adhesivity, and removing the protective film.Type: ApplicationFiled: October 25, 2010Publication date: June 9, 2011Inventors: Yun-Ho KOOK, Chul-Ho KIM, Sang-Chul JUNG, Jeong-Hoon LEE, Nam-Kook KIM, Jun-Young YANG
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Patent number: 7833837Abstract: A chip scale package includes a patterned circuit layer attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive layer such that contact pads on a lower surface of the patterned circuit layer are electrically coupled to corresponding bonding pads on the semiconductor chip. The patterned circuit layer has a plurality of openings formed therein at locations corresponding to the contact pads such that each of the contact pads has a portion exposed from an upper surface of the patterned circuit layer through the corresponding opening. A plurality of metal bumps are respectively disposed in the openings and mounted to the exposed portions of the contact pads for making external electrical connection. The present invention further provides a method for manufacturing the chip scale package at the wafer-level.Type: GrantFiled: June 4, 2007Date of Patent: November 16, 2010Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Jun Young Yang, You Ock Joo, Dong Pil Jung
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Patent number: 7700411Abstract: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The present invention further provides methods for manufacturing the semiconductor device package.Type: GrantFiled: September 7, 2007Date of Patent: April 20, 2010Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Jun Young Yang, You Ock Joo, Dong Pil Jung
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Patent number: 7656047Abstract: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The electromagnetic interference shielding layer is a plated metal layer in contact with the package body, and the plated metal layer is connected to a ground trace extending on the upper surface of the substrate.Type: GrantFiled: September 7, 2007Date of Patent: February 2, 2010Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Jun Young Yang, You Ock Joo, You Pil Jung
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Patent number: 7633170Abstract: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The present invention further provides methods for manufacturing the semiconductor device package.Type: GrantFiled: January 5, 2005Date of Patent: December 15, 2009Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Jun Young Yang, You Ock Joo, Dong Pil Jung
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Patent number: 7439098Abstract: A semiconductor package comprises a silicon substrate having an insulative surface; a patterned metal layer, formed on the insulative surface of the silicon substrate; an insulation layer formed on the patterned metal layer, and the patterned metal layer being partially exposed for functioning as at least a set of the device attaching pads and ball attaching pads; at least a device electrically connected to the set of the device attaching pads; a sealing compound for covering portions of the insulative surface of the silicon substrate and encapsulating the devices; and a plurality of solder balls attached to the set of ball attaching pads.Type: GrantFiled: September 9, 2005Date of Patent: October 21, 2008Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Jun-Young Yang, Tae-Seog Kim, You-Ock Joo
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Publication number: 20080174013Abstract: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The present invention further provides methods for manufacturing the semiconductor device package.Type: ApplicationFiled: February 27, 2008Publication date: July 24, 2008Inventors: Jun Young YANG, You Ock JOO, Dong Pil JUNG
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Publication number: 20080042301Abstract: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The electromagnetic interference shielding layer is a plated metal layer in contact with the package body, and the plated metal layer is connected to a ground trace extending on the upper surface of the substrate.Type: ApplicationFiled: September 7, 2007Publication date: February 21, 2008Applicants: ENGINEERING, INC.Inventors: Jun Young Yang, You Joo, You Pil Jung
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Publication number: 20070272727Abstract: A die pick and place tool is used to pick up a semiconductor die and place it on a substrate. The die pick and place tool comprises a moving shaft, an adjustable bearing or an elastic element, and a pick-up head. The adjustable bearing or the elastic element is connected to the moving shaft. The pick-up head is connected to the adjustable bearing, and used to catch the semiconductor die. When the semiconductor die contacts the substrate, a counter force acts to the adjustable bearing to adjust the tilt level of the pick-up head.Type: ApplicationFiled: December 4, 2006Publication date: November 29, 2007Inventor: Jun-Young Yang