Patents by Inventor Juri H. Krieger
Juri H. Krieger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8710628Abstract: An embodiment of the present memory cell a first layer of a chosen conductivity type, and a second layer which includes ferroelectric semiconductor material of the opposite conductivity type, the layers forming a pn junction. The first layer may be a conjugated semiconductor polymer, or may also be of ferroelectric semiconductor material. The layers are provided between first and electrodes. In another embodiment, a single layer of a composite of conjugated semiconductor polymer and ferroelectric semiconductor material is provided between first and second electrodes. The various embodiments may be part of a memory array.Type: GrantFiled: December 9, 2011Date of Patent: April 29, 2014Assignee: Spansion LLCInventor: Juri H. Krieger
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Publication number: 20120080773Abstract: An embodiment of the present memory cell a first layer of a chosen conductivity type, and a second layer which includes ferroelectric semiconductor material of the opposite conductivity type, the layers forming a pn junction. The first layer may be a conjugated semiconductor polymer, or may also be of ferroelectric semiconductor material. The layers are provided between first and electrodes. In another embodiment, a single layer of a composite of conjugated semiconductor polymer and ferroelectric semiconductor material is provided between first and second electrodes. The various embodiments may be part of a memory array.Type: ApplicationFiled: December 9, 2011Publication date: April 5, 2012Inventor: Juri H. KRIEGER
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Patent number: 8089110Abstract: An embodiment of the present memory cell includes a first layer of a chosen conductivity type, and a second layer which includes ferroelectric semiconductor material of the opposite conductivity type, the layers forming a pn junction. The first layer may be a conjugated semiconductor polymer, or may also be of ferroelectric semiconductor material. The layers are provided between first and second electrodes. In another embodiment, a single layer of a composite of conjugated semiconductor polymer and ferroelectric semiconductor material is provided between first and second electrodes. The various embodiments may be part of a memory array.Type: GrantFiled: February 9, 2006Date of Patent: January 3, 2012Assignee: Spansion LLCInventor: Juri H. Krieger
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Patent number: 7981773Abstract: Systems and methodologies are provided for forming a diode component integral with a memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a PN junction of memory cell having a passive and active layer with asymmetric semiconducting properties. Such an arrangement reduces a number of transistor-type voltage controls and associated power consumption, while enabling individual memory cell programming as part of a passive array. Moreover, the system provides for an efficient placement of memory cells on a wafer surface, and increases an amount of die space available for circuit design.Type: GrantFiled: May 22, 2009Date of Patent: July 19, 2011Assignee: Spansion LLCInventors: Juri H. Krieger, Stuart Spitzer
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Patent number: 7776682Abstract: Disclosed are methods and systems for improving cell-to-cell repeatability of electrical performance in memory cells. The methods involve forming an electrically non-conducting material having ordered porosity over a passive layer. The ordered porosity can facilitate formation of conductive channels through which charge carriers can migrate across the otherwise non-conductive layer to facilitate changing a state of a memory cell. A barrier layer can optionally be formed over the non-conductive layer, and can have ordered porosity oriented in a manner substantially perpendicular to the conductive channels such that charge carries migrating across the non-conductive layer cannot permeate the barrier layer. The methods provide for the manufacture of microelectronic devices with cost-effective and electrically reliable memory cells.Type: GrantFiled: April 20, 2005Date of Patent: August 17, 2010Assignees: Spansion LLC, GlobalFoundries Inc.Inventors: Alexander Nickel, Suzette K. Pangrle, Steven C. Avanzino, Jeffrey Shields, Fei Wang, Minh Tran, Juri H. Krieger, Igor Sokolik
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Publication number: 20090233422Abstract: Systems and methodologies are provided for forming a diode component integral with a memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a PN junction of memory cell having a passive and active layer with asymmetric semiconducting properties. Such an arrangement reduces a number of transistor-type voltage controls and associated power consumption, while enabling individual memory cell programming as part of a passive array. Moreover, the system provides for an efficient placement of memory cells on a wafer surface, and increases an amount of die space available for circuit design.Type: ApplicationFiled: May 22, 2009Publication date: September 17, 2009Applicant: SPANSION LLCInventors: Juri H. Krieger, Stuart Spitzer
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Patent number: 7550761Abstract: Systems and methodologies are provided for forming a diode component integral with a memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a PN junction of memory cell having a passive and active layer with asymmetric semiconducting properties. Such an arrangement reduces a number of transistor-type voltage controls and associated power consumption, while enabling individual memory cell programming as part of a passive array. Moreover, the system provides for an efficient placement of memory cells on a wafer surface, and increases an amount of die space available for circuit design.Type: GrantFiled: December 26, 2006Date of Patent: June 23, 2009Assignee: Spansion LLCInventors: Juri H. Krieger, Stuart Spitzer
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Patent number: 7307338Abstract: Systems and methodologies are provided for forming three dimensional memory structures that are fabricated from blocks of individual polymer memory cells stacked on top of each other. Such a polymer memory structure can be formed on top of control component circuitries employed for programming a plurality of memory cells that form the stacked three dimensional structure. Such an arrangement provides for an efficient placement of polymer memory cell on a wafer surface, and increases amount of die space available for circuit design.Type: GrantFiled: July 26, 2004Date of Patent: December 11, 2007Assignee: Spansion LLCInventors: Aaron Mandell, Juri H Krieger, Igor Sokolik, Richard P Kingsborough, Stuart Spitzer
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Patent number: 7295461Abstract: A memory device with multi-bit memory cells and method of making the same uses self-assembly to provide polymer memory cells on the contacts to a transistor array. Employing self-assembly produces polymer memory cells at the precise locations of the contacts of the transistor array. The polymer memory cells change resistance values in response to electric current above a specified threshold value. The memory cells retain the resistivity values over time.Type: GrantFiled: October 4, 2004Date of Patent: November 13, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Juri H Krieger, Nicolay F Yudanov
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Patent number: 7289353Abstract: Systems and methodologies are provided for adjusting threshold associated with a polymer memory cell's operation by applying thereupon a regulated electric field and/or voltage pulse width, during a post fabrication stage. Such customization of programming thresholds can typically be obtained at any cycle of programming the memory cell, to increase flexibility in circuit design. Accordingly, the present invention supplies both a current-voltage domain, and/or a frequency-time domain, to facilitate adjusting the program thresholds of the polymer memory cell.Type: GrantFiled: August 17, 2004Date of Patent: October 30, 2007Assignee: Spansion, LLCInventors: Stuart Spitzer, Juri H Krieger, David Gaun
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Patent number: 7221599Abstract: Systems and methodologies are provided for activating a polymer memory cell(s) after production by subjecting the polymer memory cell to an electrical field, for an initialization thereof. Such initialization can facilitate the distribution and mobility of metal ions (or charged metallic molecules) within an active layer of the polymer memory cell. The memory cell can include various layers of alternating passive and active media, which are sandwiched between conducting electrode layers.Type: GrantFiled: November 1, 2004Date of Patent: May 22, 2007Assignee: Spansion, LLCInventors: David Gaun, Juri H Krieger, Stuart Spitzer
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Patent number: 7199394Abstract: Systems and methodologies are provided for of enabling a polymer memory cell to exhibit variable retention times for stored data therein. Such setting of retention time can depend upon a programming mode and/or type of material employed in the polymer memory cell. Short retention times can be obtained by programming the polymer memory cell via a low current or a low electrical field. Similarly, long retention times can be obtained by employing a high current or electrical field to program the polymer memory cell.Type: GrantFiled: August 17, 2004Date of Patent: April 3, 2007Assignee: Spansion LLCInventors: Aaron Mandell, Michael A VanBuskirk, Stuart Spitzer, Juri H Krieger
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Patent number: 7157732Abstract: Systems and methodologies are provided for forming a diode component integral with a memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a PN junction of memory cell having a passive and active layer with asymmetric semiconducting properties. Such an arrangement reduces a number of transistor-type voltage controls and associated power consumption, while enabling individual memory cell programming as part of a passive array. Moreover, the system provides for an efficient placement of memory cells on a wafer surface, and increases an amount of die space available for circuit design.Type: GrantFiled: July 1, 2004Date of Patent: January 2, 2007Assignee: Spansion LLCInventors: Juri H. Krieger, Stuart Spitzer
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Patent number: 7113420Abstract: A memory cell is provided with a pair of electrodes, and an active layer sandwiched between the electrodes and including a molecular system and ionic complexes distributed in the molecular system. The active layer having a high-impedance state and a low-impedance state switches from the high-impedance state to the low-impedance state when an amplitude of a writing signal exceeds a writing threshold level, to enable writing information into the memory cell. The active layer switches from the low-impedance state to the high-impedance state when an amplitude of an erasing signal having opposite polarity with respect to the writing signal exceeds an erasing threshold level, to enable erasing information from the memory cell.Type: GrantFiled: January 12, 2005Date of Patent: September 26, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Juri H Krieger, Nicolay F Yudanov
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Patent number: 6873540Abstract: A memory cell is provided with a pair of electrodes, and an active layer sandwiched between the electrodes and including a molecular system and ionic complexes distributed in the molecular system. The active layer having a high-impedance state and a low-impedance state switches from the high-impedance state to the low-impedance state when an amplitude of a writing signal exceeds a writing threshold level, to enable writing information into the memory cell. The active layer switches from the low-impedance state to the high-impedance state when an amplitude of an erasing signal having opposite polarity with respect to the writing signal exceeds an erasing threshold level, to enable erasing information from the memory cell.Type: GrantFiled: May 7, 2002Date of Patent: March 29, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Juri H. Krieger, Nikolay F. Yudanov
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Patent number: 6864522Abstract: A memory storage and retrieval device containing (a) an electrically conductive first electrode; (b) an electrically conductive second electrode; (c) a layer stack intermediate the first and second electrodes containing (d) at least one active layer with variable electrical conductivity; and (e) at least one passive layer containing a source material for varying the electrical conductivity of the at least one active layer upon application of an electrical potential difference between the first and second electrodes.Type: GrantFiled: April 15, 2003Date of Patent: March 8, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Juri H. Krieger, Nikolai Yudanoy
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Patent number: 6858481Abstract: A memory including memory cells having active and passive layers may store multiple information bits. The active layer may include an organic polymer that has a variable resistance based on the movement of charged species (ions or ions and electrons) between the passive layer and the active layer. The passive layer may be a super-ionic material that has high ion and electron mobility. The active layer may be self-assembled from a monomer in a liquid or gas.Type: GrantFiled: April 15, 2003Date of Patent: February 22, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Juri H. Krieger, Nikolai Yudanov
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Patent number: 6855977Abstract: A memory device with multi-bit memory cells and method of making the same uses self-assembly to provide polymer memory cells on the contacts to a transistor array. Employing self-assembly produces polymer memory cells at the precise locations of the contacts of the transistor array. The polymer memory cells change resistance values in response to electric current above a specified threshold value. The memory cells retain the resistivity values over time.Type: GrantFiled: May 7, 2002Date of Patent: February 15, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Juri H. Krieger, N. F. Yudanov
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Patent number: 6838720Abstract: A memory including memory cells having active and passive layers may store multiple information bits. The active layer may include an organic polymer that has a variable resistance based on the movement of charged species (ions or ions and electrons) between the passive layer and the active layer. The passive layer may be a super-ionic material that has high ion and electron mobility. The active layer may be self-assembled from a monomer in a liquid or gas.Type: GrantFiled: April 15, 2003Date of Patent: January 4, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Juri H. Krieger, Nikolai Yudanov
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Patent number: 6815286Abstract: A method of forming and operating a memory storage and retrieval device containing (a) an electrically conductive first electrode; (b) an electrically conductive second electrode; (c) a layer stack intermediate the first and second electrodes containing (d) at least one active layer with variable electrical conductivity; and (e) at least one passive layer containing a source material for varying the electrical conductivity of the at least one active layer upon application of an electrical potential difference between the first and second electrodes.Type: GrantFiled: September 11, 2002Date of Patent: November 9, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Juri H. Krieger, Nikolai Yudanov