Patents by Inventor Juri Kato

Juri Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7687866
    Abstract: A semiconductor device includes a semiconductor layer formed partially on a semiconductor substrate by epitaxial growth, an embedded oxide film embedded between the semiconductor substrate and the semiconductor layer, first and second gate electrodes disposed on sidewalls of the semiconductor layer, a source layer formed in the semiconductor layer and disposed in the first gate electrode, and a drain layer formed in the semiconductor layer and disposed in the second gate electrode, wherein the sidewalls of the semiconductor layer are film-forming surfaces of the epitaxial growth.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: March 30, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Juri Kato
  • Patent number: 7666795
    Abstract: A method for manufacturing a semiconductor device includes forming a SiGe layer on a Si substrate, forming a dummy pattern to expose a surface of the Si substrate, and wet etching the SiGe layer while an etchant is contacted with, the dummy pattern.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: February 23, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Juri Kato, Hideaki Oka, Masamitsu Uehara
  • Patent number: 7638845
    Abstract: A semiconductor device includes a first insulator formed at a part under a semiconductor layer, a second insulator formed under the semiconductor layer in an arranged manner avoiding the first insulator and having a relative dielectric constant different from that of the first insulator, a backgate electrode formed under the first and second insulators, a gate electrode formed on the semiconductor layer, and a source layer and a drain layer formed in the semiconductor layer to be respectively arranged on opposite lateral sides of the gate electrode.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: December 29, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Juri Kato
  • Patent number: 7622359
    Abstract: A method for manufacturing a semiconductor device, includes: (a) forming a SiGe layer on a Si substrate; (b) forming a Si layer on the SiGe layer; (c) forming a dummy pattern made of SiGe in a dummy region of the Si substrate; and (d) wet-etching and removing the SiGe layer formed under the Si layer. In the step (d), an etchant is kept to contact the dummy pattern from before a complete remove of the SiGe layer to an end of the etching.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: November 24, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Juri Kato, Kei Kanemoto
  • Patent number: 7563665
    Abstract: To laminate field effect transistors having different conductivity types, while suppressing deterioration of the crystallinity of semiconductor layers where the field effect transistors are formed. A single crystal semiconductor layer, a dielectric layer and a single crystal semiconductor layer are successively laminated on a dielectric layer, a gate electrode is formed on side walls on both sides of the single crystal semiconductor layers through gate dielectric films and formed on side surfaces on both side of the single crystal semiconductor layers, source/drain layers disposed respectively on both sides of the gate electrode are formed in the single crystal semiconductor layer 13a, and source/drain layers disposed respectively on both sides of the gate electrode are formed in the single crystal semiconductor layer, whereby a P-channel field effect transistor MP1 and an N-channel field effect transistor MN1 are laminated.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: July 21, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Juri Kato
  • Patent number: 7491609
    Abstract: A semiconductor device includes a gate electrode formed on a semiconductor layer, source and drain layers formed in the semiconductor layer and disposed on both sides of the gate electrode, and a field plate disposed at the back of the semiconductor layer with an insulating layer provided therebetween.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: February 17, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Juri Kato
  • Patent number: 7425484
    Abstract: A method of manufacturing a semiconductor device includes forming on a semiconductor substrate, a plurality of multi-layered structures each including a first semiconductor layer and a second semiconductor layer that is deposited over the first semiconductor layer and has an etching rate smaller than the etching rate of the first semiconductor layer, forming a first trench through the first semiconductor layer and the second semiconductor layer, forming a support body on sidewalls of the first semiconductor layer and the second semiconductor layer in the first trench, forming a second trench that exposes through the second semiconductor layer, etching the first semiconductor layer via the second trench selectively, to form under the second semiconductor layer, a cavity resulting from removal of the first semiconductor layer, forming a buried insulating layer that is buried in the cavity, exposing a side surface of the deposited second semiconductor layer, forming a gate insulating film on the exposed side sur
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: September 16, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Juri Kato
  • Publication number: 20080203521
    Abstract: A semiconductor substrate comprising: a semiconductor base; dielectric layers of mutually different film thicknesses formed on the semiconductor base; and semiconductor layers of mutually different film thicknesses formed on the dielectric layers.
    Type: Application
    Filed: March 6, 2008
    Publication date: August 28, 2008
    Applicant: Seiko Epson Corporation
    Inventor: Juri Kato
  • Publication number: 20080194082
    Abstract: A method for manufacturing a semiconductor device, includes: (a) forming a SiGe layer on a Si substrate; (b) forming a Si layer on the SiGe layer; (c) forming a dummy pattern made of SiGe in a dummy region of the Si substrate; and (d) wet-etching and removing the SiGe layer formed under the Si layer. In the step (d), an etchant is kept to contact the dummy pattern from before a complete remove of the SiGe layer to an end of the etching.
    Type: Application
    Filed: February 4, 2008
    Publication date: August 14, 2008
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Juri KATO, Kei KANEMOTO
  • Publication number: 20080180186
    Abstract: A method for manufacturing a piezoelectric oscillator includes the steps of: forming a first semiconductor layer above a substrate; forming a second semiconductor layer above the first semiconductor layer; forming a first opening section that exposes the substrate by removing the second semiconductor layer and the first semiconductor layer in an area for forming a support section; forming the support section in the first opening section; forming a driving section that generates flexing vibration in an oscillation section above the second semiconductor layer; patterning the second semiconductor layer to form the oscillation section having the supporting section as a base end and another end provided so as not to contact the supporting section, and a second opening section that exposes the first semiconductor layer; and removing the first semiconductor layer through a portion exposed at the second opening section by an etching method, thereby forming a cavity section at least below the oscillation section, wher
    Type: Application
    Filed: January 24, 2008
    Publication date: July 31, 2008
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Takamitsu HIGUCHI, Juri KATO, Yasuhiro ONO
  • Publication number: 20080176385
    Abstract: A method of manufacturing a semiconductor device, comprises; a) forming a SiGe layer on a substrate; b) forming a Si layer on the SiGe layer ; c) forming a groove that exposes the side surface of the SiGe layer by partly etching the Si layer and the SiGe layer; and d) forming a hollow portion between the substrate and, the Si layer by etching the SiGe layer via the groove. Step d) further comprises: forming a part of the hollow portion by supplying a new liquid including a fluorinated nitric acid solution to the substrate and etching the SiGe layer, removing the fluorinated nitric acid solution once from the hollow portion that is under formation; and etching the SiGe layer by refilling a new liquid including a fluorinated nitric acid solution to the hollow portion.
    Type: Application
    Filed: November 29, 2007
    Publication date: July 24, 2008
    Applicants: SEIKO EPSON CORPORATION, TOKYO INSTITUTE OF TECHNOLOGY
    Inventors: Juri KATO, Shunichiro OHMI
  • Publication number: 20080145999
    Abstract: A method of a semiconductor device comprises: a) depositing a first semiconductor layer and a second semiconductor layer in a semiconductor substrate in series; b) forming a first groove penetrating the first and second semiconductor layers and placed adjacent to an element region by partly etching the first and second semiconductor layers; c) forming a supporting member that supports the second semiconductor layer and covers over the second semiconductor layer and is embedded into the first groove; d) forming a second groove that exposes the first semiconductor layer from the bottom of the second semiconductor layer supported by the supporting member and is placed near the element region; and e) forming a cavity between the semiconductor substrate and the second semiconductor layer in the element region by etching the first semiconductor layer via the second groove under a specific condition in which the first semiconductor layer is easily etched, compared to the second semiconductor layer.
    Type: Application
    Filed: December 12, 2007
    Publication date: June 19, 2008
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Juri KATO
  • Publication number: 20080146017
    Abstract: A method for manufacturing a semiconductor device comprises: (a) stacking a first semiconductor layer and a second semiconductor layer serially on a semiconductor substrate; (b) providing a protection film above the second semiconductor layer; (c) providing a first groove that penetrates the protection film, the second semiconductor layer, and the first semiconductor layer and surrounds an element region in plan view so as to define a boundary between the element region and a remaining region, by partially etching the protection film, the second semiconductor layer, and the first semiconductor layer; (d) providing a support film so as to fill the first groove and cover the second semiconductor layer; (e) providing a second groove that provides a support including the support film and exposes the first semiconductor layer from under the second semiconductor layer, by partially etching the support film in a condition that the support film is more readily etched than the protection film; and (f) providing a cavi
    Type: Application
    Filed: December 12, 2007
    Publication date: June 19, 2008
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Juri KATO
  • Publication number: 20080146035
    Abstract: A method for manufacturing a semiconductor device includes forming a SiGe layer on a Si substrate, forming a dummy pattern to expose a surface of the Si substrate, and wet etching the SiGe layer while an etchant is contacted with, the dummy pattern.
    Type: Application
    Filed: December 13, 2007
    Publication date: June 19, 2008
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Juri KATO, Hideaki OKA, Masamitsu UEHARA
  • Publication number: 20080128787
    Abstract: A semiconductor device includes a substrate, a first insulating film, a first semiconductor layer disposed above the substrate with the first insulating film therebetween, a second semiconductor layer disposed above the first semiconductor layer with a second insulating film therebetween, a first conductivity type metal oxide semiconductor (MOS) disposed on at least one side surface of the first semiconductor layer, a second conductivity type MOS disposed on at least one side surface of the second semiconductor layer, a charge storage layer common to the first and second MOS transistors, and a control gate common to the first and second MOS transistors. The common charge storage layer is continuously provided from the side surface of the first semiconductor layer on which the first conductivity type MOS transistor is disposed to the side surface of the second semiconductor layer on which the second conductivity type MOS transistor is disposed.
    Type: Application
    Filed: November 30, 2007
    Publication date: June 5, 2008
    Applicant: Seiko Epson Corporation
    Inventor: Juri Kato
  • Publication number: 20080122024
    Abstract: A semiconductor substrate comprising a semiconductor base, a dielectric layer formed in at least a part of an area on the semiconductor base, and a single crystal semiconductor layers having mutually different film thicknesses, disposed on the dielectric layer and formed by epitaxial growth.
    Type: Application
    Filed: January 24, 2008
    Publication date: May 29, 2008
    Applicant: Seiko Epson Corporation
    Inventor: Juri Kato
  • Patent number: 7368340
    Abstract: A semiconductor device includes a semiconductor substrate in which an insulating layer is formed in a part of an region, a semiconductor layer is formed by epitaxial growth and located on the insulating layer, a first gate electrode is formed at the sidewall of the semiconductor layer, first source and drain regions are formed in the semiconductor layer and located at the side of the first gate electrode, a second electrode is formed on the semiconductor substrate, and second source and drain regions are formed in the semiconductor substrate and located at the side of the second gate electrode.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: May 6, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Juri Kato
  • Patent number: 7351616
    Abstract: A semiconductor substrate comprising: a semiconductor base; dielectric layers of mutually different film thicknesses formed on the semiconductor base; and semiconductor layers of mutually different film thicknesses formed on the dielectric layers.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: April 1, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Juri Kato
  • Patent number: 7344997
    Abstract: A semiconductor substrate comprising a semiconductor base, a dielectric layer formed in at least a part of an area on the semiconductor base, and a single crystal semiconductor layers having mutually different film thicknesses, disposed on the dielectric layer and formed by epitaxial growth.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: March 18, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Juri Kato
  • Patent number: 7332399
    Abstract: A method of manufacturing semiconductor substrates. After supporting layers are provided on side walls of grooves formed in a semiconductor substrate, grooves that expose a second semiconductor layer are formed. Etching gas or etching liquid is brought in contact with the first semiconductor layer through the grooves, to form a void portion between the semiconductor substrate 1 and the second semiconductor layer. By thermally oxidizing the semiconductor substrate, the second semiconductor layer and the supporting layers, an oxide film is formed in the void portion between the semiconductor substrate and the second semiconductor layer, an oxide film is formed on side walls of the semiconductor substrate in the grooves, and the supporting layers are changed into oxide films.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: February 19, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Juri Kato