Patents by Inventor Justin Weber

Justin Weber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210083122
    Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g., <450° C.). The 2D material may be a chalcogenide of a metal present in the channel material (e.g., ZnSx or ZnSex) or of a metal absent from the channel material when formed from a sacrificial precursor.
    Type: Application
    Filed: September 13, 2019
    Publication date: March 18, 2021
    Applicant: Intel Corporation
    Inventors: Carl Naylor, Abhishek Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan, Justin Weber
  • Publication number: 20200411692
    Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Gilbert Dewey, Abhishek Sharma, Van Le, Jack Kavalieros, Shriram Shivaraman, Seung Hoon Sung, Tahir Ghani, Arnab Sen Gupta, Nazila Haratipour, Justin Weber
  • Publication number: 20200105891
    Abstract: Embodiments include transistor devices and a method of forming the transistor devices. A transistor device includes a first conductive layer over a substrate, a first transistor having first interconnects in the first conductive layer, and a second conductive layer on an insulating layer that is on the first conductive layer. The transistor device also includes a second transistor having second interconnects in the second conductive layer, and a gate electrode over the substrate, where the gate electrode has a workfunction metal that surrounds the first and second interconnects. The first and second conductive layers may include conductive materials such as an epitaxial (EPI) layer, a metal layer, or a doped-semiconductor layer. The transistor device may further include a dielectric surrounding the interconnects as the dielectric is surrounded with the workfunction metal, and a transition layer disposed between the dielectric and interconnects. The dielectric may include a high-k dielectric material.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Inventors: Aaron LILAK, Willy RACHMADY, Rishabh MEHANDRU, Gilbert DEWEY, Justin WEBER
  • Publication number: 20200098874
    Abstract: Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventors: Justin WEBER, Harold KENNEL, Abhishek SHARMA, Christopher JEZEWSKI, Matthew V. METZ, Tahir GHANI, Jack T. KAVALIEROS, Benjamin CHU-KUNG, Van H. LE, Arnab SEN GUPTA
  • Publication number: 20200098875
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a contact electrode having a conductive material above the substrate, an epitaxial layer above the contact electrode, and a channel layer including a channel material above the epitaxial layer and above the contact electrode. The channel layer is in contact at least partially with the epitaxial layer. A conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material of the contact electrode. A bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material. Furthermore, a gate electrode is above the channel layer, and separated from the channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Seung Hoon SUNG, Justin WEBER, Matthew METZ, Arnab SEN GUPTA, Abhishek SHARMA, Benjamin CHU-KUNG, Gilbert DEWEY, Charles KUO, Nazila HARATIPOUR, Shriram SHIVARAMAN, Van H. LE, Tahir GHANI, Jack T. KAVALIEROS, Sean MA
  • Publication number: 20200098887
    Abstract: Embodiments herein describe techniques for a transistor above the substrate. The transistor includes a first gate dielectric layer with a first gate dielectric material above a gate electrode, and a second dielectric layer with a second dielectric material above a portion of the first gate dielectric layer. A first portion of a channel layer overlaps with only the first gate dielectric layer, while a second portion of the channel layer overlaps with the first gate dielectric layer and the second dielectric layer. A first portion of a contact electrode overlaps with the first portion of the channel layer, and overlaps with only the first gate dielectric layer, while a second portion of the contact electrode overlaps with the second portion of the channel layer, and overlaps with the first gate dielectric layer and the second dielectric layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Gilbert DEWEY, Van H. LE, Abhishek SHARMA, Jack T. KAVALIEROS, Sean MA, Seung Hoon SUNG, Nazila HARATIPOUR, Tahir GHANI, Justin WEBER, Shriram SHIVARAMAN
  • Publication number: 20200006570
    Abstract: Embodiments of the present disclosure are contact structures for thin film transistor (TFT) devices. One embodiment is a TFT device comprising: a substrate; a gate formed above the substrate; a TFT channel formed above the substrate; and a pair of contacts formed on the TFT channel, wherein each of the contacts comprises one or more layers including: a metal that is non-reactive with a material of the TFT channel; or a plurality of layers including a first metal layer formed on a second layer, the second layer in contact with the TFT channel and between the first mater layer and the TFT channel. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Van H. LE, Rajat PAUL, Abhishek SHARMA, Tahir GHANI, Jack KAVALIEROS, Gilbert DEWEY, Matthew METZ, Miriam RESHOTKO, Benjamin CHU-KUNG, Justin WEBER, Shriram SHIVARAMAN
  • Publication number: 20190393249
    Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor above a substrate, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor includes a first channel layer above the substrate, and a first gate electrode above the first channel layer. The insulator layer is next to a first source electrode of the first transistor above the first channel layer, next to a first drain electrode of the first transistor above the first channel layer, and above the first gate electrode. The second transistor includes a second channel layer above the insulator layer, and a second gate electrode separated from the second channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 26, 2019
    Inventors: Aaron LILAK, Justin WEBER, Harold KENNEL, Willy RACHMADY, Gilbert DEWEY, Van H. LE, Abhishek SHARMA, Patrick MORROW
  • Patent number: 10273005
    Abstract: A retention system for use within a molecular sieve unit includes a perforated plate having a top face and bottom face. The perforated plate is configured to be positioned atop a packed sieve bed proximate an outlet end cap of the molecular sieve unit. A skirt is coupled to the bottom face of the perforated plate and a biasing member is configured to engage the outlet end cap and the top face of the perforated plate. The biasing member urges the perforated plate against the packed sieve bed. The biasing member may be one or more wave springs thereby reducing the risk of losing sufficient biasing force against the perforated plate. In the event that a sufficient biasing force is lost, the skirt may operate as a failsafe so as to minimize or prevent tilting of the perforated plate within the housing.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: April 30, 2019
    Assignee: Carleton Life Support Systems, Inc.
    Inventors: Todd Buenting, Lane Dicken, Justin Weber
  • Publication number: 20170291708
    Abstract: A retention system for use within a molecular sieve unit includes a perforated plate having a top face and bottom face. The perforated plate is configured to be positioned atop a packed sieve bed proximate an outlet end cap of the molecular sieve unit. A skirt is coupled to the bottom face of the perforated plate and a biasing member is configured to engage the outlet end cap and the top face of the perforated plate. The biasing member urges the perforated plate against the packed sieve bed. The biasing member may be one or more wave springs thereby reducing the risk of losing sufficient biasing force against the perforated plate. In the event that a sufficient biasing force is lost, the skirt may operate as a failsafe so as to minimize or prevent tilting of the perforated plate within the housing.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 12, 2017
    Applicant: Carleton Life Support Systems Inc.
    Inventors: Todd Buenting, Lane Dicken, Justin Weber