Abstract: Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure are contact structures for thin film transistor (TFT) devices. One embodiment is a TFT device comprising: a substrate; a gate formed above the substrate; a TFT channel formed above the substrate; and a pair of contacts formed on the TFT channel, wherein each of the contacts comprises one or more layers including: a metal that is non-reactive with a material of the TFT channel; or a plurality of layers including a first metal layer formed on a second layer, the second layer in contact with the TFT channel and between the first mater layer and the TFT channel. Other embodiments may be disclosed and/or claimed.

Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor above a substrate, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor includes a first channel layer above the substrate, and a first gate electrode above the first channel layer. The insulator layer is next to a first source electrode of the first transistor above the first channel layer, next to a first drain electrode of the first transistor above the first channel layer, and above the first gate electrode. The second transistor includes a second channel layer above the insulator layer, and a second gate electrode separated from the second channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

Abstract: A retention system for use within a molecular sieve unit includes a perforated plate having a top face and bottom face. The perforated plate is configured to be positioned atop a packed sieve bed proximate an outlet end cap of the molecular sieve unit. A skirt is coupled to the bottom face of the perforated plate and a biasing member is configured to engage the outlet end cap and the top face of the perforated plate. The biasing member urges the perforated plate against the packed sieve bed. The biasing member may be one or more wave springs thereby reducing the risk of losing sufficient biasing force against the perforated plate. In the event that a sufficient biasing force is lost, the skirt may operate as a failsafe so as to minimize or prevent tilting of the perforated plate within the housing.

Abstract: A retention system for use within a molecular sieve unit includes a perforated plate having a top face and bottom face. The perforated plate is configured to be positioned atop a packed sieve bed proximate an outlet end cap of the molecular sieve unit. A skirt is coupled to the bottom face of the perforated plate and a biasing member is configured to engage the outlet end cap and the top face of the perforated plate. The biasing member urges the perforated plate against the packed sieve bed. The biasing member may be one or more wave springs thereby reducing the risk of losing sufficient biasing force against the perforated plate. In the event that a sufficient biasing force is lost, the skirt may operate as a failsafe so as to minimize or prevent tilting of the perforated plate within the housing.