Patents by Inventor Juwen Gao

Juwen Gao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250149383
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.
    Type: Application
    Filed: November 11, 2024
    Publication date: May 8, 2025
    Inventors: Anand CHANDRASHEKAR, Esther JENG, Raashina HUMAYUN, Michal DANEK, Juwen GAO, Deqi WANG
  • Publication number: 20250051908
    Abstract: Methods of filling a feature with large grain tungsten include deposition of a tungsten carbon nitride (WCN) or tungsten nitride (WN) film that lines the feature. The WCN or WN film may be treated. It provides a template for subsequent growth of large grain tungsten. The top of the feature is treated with nitrogen to inhibit nucleation, facilitating bottom-up growth. In some embodiments, single grain tungsten is grown from the bottom up. Methods of at least partially filling a feature with single grain tungsten include treatment of the feature. In some embodiments, single grain tungsten is grown without a liner layer in the feature.
    Type: Application
    Filed: December 9, 2022
    Publication date: February 13, 2025
    Inventors: Kevin Qiwen CHEN, Yu PAN, Chan Myae Myae SOE, Esther JENG, Juwen GAO
  • Publication number: 20250022751
    Abstract: Methods of filling a features of partially fabricated semiconductor substrates with metal include depositing a gradient metal nitride layer in the feature. The gradient metal nitride layer decreases in thickness and/or nitrogen concentration with feature depth. At the top of the feature, the gradient metal nitride layer can serve as an adhesion layer during a subsequent planarization. Because the gradient metal nitride layer deceases in thickness and/or nitrogen concentration further into the feature, it occupies less volume in the mid-section and bottom section of the feature. This improves resistivity in the feature. The feature is filled with metal.
    Type: Application
    Filed: November 30, 2022
    Publication date: January 16, 2025
    Inventors: Sang-Hyeob LEE, Anand CHANDRASHEKAR, Kaihan Abidi ASHTIANI, Patrick August VAN CLEEMPUT, Joshua COLLINS, Lawrence SCHLOSS, Sanjay GOPINATH, Juwen GAO
  • Publication number: 20240282580
    Abstract: Described herein are methods and apparatuses for filling semiconductor substrate structures with conductive material. The methods involve depositing multi-layer bulk metal films in structures with one or more deposition conditions changed when transitioning from layer-to-layer. The methods result in high fill quality, high throughput, low precursor consumption, and low roughness. Multi-station chambers to perform the methods are also provided.
    Type: Application
    Filed: May 3, 2024
    Publication date: August 22, 2024
    Inventors: Xiaolan BA, Ruopeng DENG, Juwen GAO, Sanjay GOPINATH, Lawrence SCHLOSS
  • Patent number: 12060639
    Abstract: Provided herein are methods and related apparatus for purging processing chambers during an atomic layer deposition (ALD) process. The methods involve flowing purging gas from one or more accumulators to remove process gases from the processing chambers. Following the flowing of purging gas, additional reactants may be introduced into the processing chamber to continue an ALD cycle.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: August 13, 2024
    Assignee: Lam Research Corporation
    Inventors: Pragna Nannapaneni, Sema Ermez, Novy Tjokro, Ruopeng Deng, Tianhua Yu, Xiaolan Ba, Juwen Gao, Sanjay Gopinath
  • Publication number: 20240266177
    Abstract: Methods and apparatuses are described that provide tungsten deposition with low roughness. In some embodiments, the methods involve co-flowing nitrogen with hydrogen during an atomic layer deposition process of depositing tungsten that uses hydrogen as a reducing agent. In some embodiments, the methods involve depositing a cap layer, such as tungsten oxide or amorphous tungsten layer, on a sidewall surface of a 3D NAND structure. The disclosed embodiments have a wide variety of applications including depositing tungsten into 3D NAND structures.
    Type: Application
    Filed: March 21, 2024
    Publication date: August 8, 2024
    Inventors: Ruopeng Deng, Xiaolan Ba, Tianhua Yu, Yu Pan, Juwen Gao
  • Patent number: 12014928
    Abstract: Described herein are methods and apparatuses for filling semiconductor substrate structures with conductive material. The methods involve depositing multi-layer bulk metal films in structures with one or more deposition conditions changed when transitioning from layer-to-layer. The methods result in high fill quality, high throughput, low precursor consumption, and low roughness. Multi-station chambers to perform the methods are also provided.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: June 18, 2024
    Assignee: Lam Research Corporation
    Inventors: Xiaolan Ba, Ruopeng Deng, Juwen Gao, Sanjay Gopinath, Lawrence Schloss
  • Patent number: 11972952
    Abstract: Methods and apparatuses are described that provide tungsten deposition with low roughness. In some embodiments, the methods involve co-flowing nitrogen with hydrogen during an atomic layer deposition process of depositing tungsten that uses hydrogen as a reducing agent. In some embodiments, the methods involve depositing a cap layer, such as tungsten oxide or amorphous tungsten layer, on a sidewall surface of a 3D NAND structure. The disclosed embodiments have a wide variety of applications including depositing tungsten into 3D NAND structures.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: April 30, 2024
    Assignee: Lam Research Corporation
    Inventors: Ruopeng Deng, Xiaolan Ba, Tianhua Yu, Yu Pan, Juwen Gao
  • Patent number: 11901227
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: February 13, 2024
    Assignee: Lam Research Corporation
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Publication number: 20240006180
    Abstract: Provided herein are methods of depositing tungsten (W) films without depositing a nucleation layer. In certain embodiments, the methods involve depositing a conformal layer of boron (B) on a substrate. The substrate generally includes a feature to be filled with tungsten with the boron layer conformal to the topography of the substrate including the feature. The reducing agent layer is then exposed to a continuous flow of hydrogen and pulses of fluorine-containing tungsten precursor in a pulsed CVD process. The conformal boron layer is converted to a conformal tungsten layer.
    Type: Application
    Filed: November 16, 2021
    Publication date: January 4, 2024
    Inventors: Yu PAN, Yao-Tsung HSIEH, Xiaolan BA, Juwen GAO
  • Publication number: 20230290639
    Abstract: Methods and apparatuses for forming low resistivity tungsten using tungsten nitride barrier layers are provided herein. Methods involve depositing extremely thin tungsten nitride barrier layers prior to depositing tungsten nucleation and bulk tungsten layers. Methods are applicable for fabricating tungsten word lines in 3D NAND fabrication as well as for fabricating tungsten-containing components of DRAM and logic fabrication. Apparatus included processing stations with multiple charge volumes to pressurize gases in close vicinity to a showerhead of a processing chamber for processing semiconductor substrates.
    Type: Application
    Filed: July 29, 2020
    Publication date: September 14, 2023
    Inventors: Lawrence Schloss, Anand Chandrashekar, Juwen Gao, Stephanie Noelle Sandra Sawant-Goubert, Yu Pan
  • Patent number: 11670516
    Abstract: Various embodiments herein relate to methods, apparatus, and systems for etching a feature in a substrate. Typically the feature is etched in a dielectric-containing stack. The etching process involves cyclically etching the feature and depositing a protective film on sidewalls of the partially etched feature. These stages are repeated until the feature reaches its final depth. The protective film may have a particular composition, for example including at least one of a tungsten carbonitride, a tungsten sulfide, tin, a tin-containing compound, molybdenum, a molybdenum-containing compound, a ruthenium carbonitride, a ruthenium sulfide, an aluminum carbonitride, an aluminum sulfide, zirconium, and a zirconium-containing compound. A number of optional steps may be taken including, for example, doping the mask layer, pre-treating the substrate prior to deposition, removing the protective film from the sidewalls, and oxidizing any remaining protective film.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: June 6, 2023
    Assignee: Lam Research Corporation
    Inventors: Karthik S. Colinjivadi, Samantha SiamHwa Tan, Shih-Ked Lee, George Matamis, Yongsik Yu, Yang Pan, Patrick Van Cleemput, Akhil Singhal, Juwen Gao, Raashina Humayun
  • Publication number: 20230041794
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.
    Type: Application
    Filed: June 28, 2022
    Publication date: February 9, 2023
    Inventors: Anand CHANDRASHEKAR, Esther JENG, Raashina Humayun, Michal DANEK, Juwen GAO, Deqi WANG
  • Patent number: 11410883
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: August 9, 2022
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Publication number: 20220186370
    Abstract: Provided herein are methods and related apparatus for purging processing chambers during an atomic layer deposition (ALD) process. The methods involve flowing purging gas from one or more accumulators to remove process gases from the processing chambers. Following the flowing of purging gas, additional reactants may be introduced into the processing chamber to continue an ALD cycle.
    Type: Application
    Filed: April 15, 2020
    Publication date: June 16, 2022
    Applicant: Lam Research Corporation
    Inventors: Pragna Nannapaneni, Sema Ermez, Novy Tjokro, Ruopeng Deng, Tianhua Yu, Xiaolan Ba, Juwen Gao, Sanjay Gopinath
  • Patent number: 11348795
    Abstract: Disclosed are methods of depositing a transition metal such as tungsten on a semiconductor substrate. The method includes providing a gas mixture of diborane with a balance of hydrogen, where the hydrogen serves to stabilize the diborane in the gas mixture. The method further includes delivering the gas mixture to the semiconductor substrate to form a boron layer, where the boron layer serves as a reducing agent layer to convert a metal-containing precursor to metal, such as a tungsten-containing precursor to tungsten. In some implementations, the semiconductor substrate includes a vertical structure, such as a three-dimensional vertical NAND structure, with horizontal features or wordlines having openings in sidewalls of the vertical structure, where the boron layer may be conformally deposited in the horizontal features of the vertical structure.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: May 31, 2022
    Assignee: Lam Research Corporation
    Inventors: Lawrence Schloss, Raashina Humayun, Sanjay Gopinath, Juwen Gao, Michal Danek, Kaihan Abidi Ashtiani
  • Publication number: 20220102208
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
    Type: Application
    Filed: October 8, 2021
    Publication date: March 31, 2022
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Publication number: 20210335617
    Abstract: Methods and apparatuses are described that provide tungsten deposition with low roughness. In some embodiments, the methods involve co-flowing nitrogen with hydrogen during an atomic layer deposition process of depositing tungsten that uses hydrogen as a reducing agent. In some embodiments, the methods involve depositing a cap layer, such as tungsten oxide or amorphous tungsten layer, on a sidewall surface of a 3D NAND structure. The disclosed embodiments have a wide variety of applications including depositing tungsten into 3D NAND structures.
    Type: Application
    Filed: December 13, 2019
    Publication date: October 28, 2021
    Inventors: Ruopeng Deng, Xiaolan Ba, Tianhua Yu, Yu Pan, Juwen Gao
  • Publication number: 20210327754
    Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).
    Type: Application
    Filed: June 25, 2021
    Publication date: October 21, 2021
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Publication number: 20210313183
    Abstract: Described herein are methods and apparatuses for filling semiconductor substrate structures with conductive material. The methods involve depositing multi-layer bulk metal films in structures with one or more deposition conditions changed when transitioning from layer-to-layer. The methods result in high fill quality, high throughput, low precursor consumption, and low roughness. Multi-station chambers to perform the methods are also provided.
    Type: Application
    Filed: July 31, 2019
    Publication date: October 7, 2021
    Inventors: Xiaolan Ba, Ruopeng Deng, Juwen Gao, Sanjay Gopinath, Lawrence Schloss