Patents by Inventor Juwen Gao

Juwen Gao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10256142
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: April 9, 2019
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Publication number: 20190019725
    Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).
    Type: Application
    Filed: September 6, 2018
    Publication date: January 17, 2019
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Patent number: 10103058
    Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: October 16, 2018
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Publication number: 20180277431
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
    Type: Application
    Filed: May 29, 2018
    Publication date: September 27, 2018
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Publication number: 20180219014
    Abstract: Disclosed herein are methods and related apparatus for formation of multi-component tungsten-containing films including multi-component tungsten-containing films diffusion barriers. According to various embodiments, the methods involve deposition of multi-component tungsten-containing films using tungsten chloride (WClx) precursors and boron (B)-containing, silicon (Si)-containing or germanium (Ge)-containing reducing agents.
    Type: Application
    Filed: March 19, 2018
    Publication date: August 2, 2018
    Inventors: Michal Danek, Hanna Bamnolker, Raashina Humayun, Juwen Gao
  • Patent number: 9997405
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 12, 2018
    Assignee: Lam Research Corporation
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Patent number: 9969622
    Abstract: Ternary tungsten boride nitride (WBN) thin films and related methods of formation are provided. The films are have excellent thermal stability, tunable resistivity and good adhesion to oxides. Methods of forming the films can involve thermal atomic layer deposition (ALD) processes in which boron-containing, nitrogen-containing and tungsten-containing reactants are sequentially pulsed into a reaction chamber to deposit the WBN films. In some embodiments, the processes include multiple cycles of boron-containing, nitrogen-containing and tungsten-containing reactant pulses, with each cycle including multiple boron-containing pulses.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: May 15, 2018
    Assignee: Lam Research Corporation
    Inventors: Wei Lei, Juwen Gao
  • Patent number: 9953984
    Abstract: Disclosed herein are methods and related apparatus for formation of tungsten wordlines in memory devices. Also disclosed herein are methods and related apparatus for deposition of fluorine-free tungsten (FFW). According to various embodiments, the methods involve deposition of multi-component tungsten films using tungsten chloride (WClx) precursors and boron (B)-containing, silicon (Si)-containing or germanium (Ge)-containing reducing agents.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: April 24, 2018
    Assignee: Lam Research Corporation
    Inventors: Michal Danek, Hanna Bamnolker, Raashina Humayun, Juwen Gao
  • Publication number: 20170278749
    Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).
    Type: Application
    Filed: April 7, 2017
    Publication date: September 28, 2017
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Patent number: 9653353
    Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: May 16, 2017
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Patent number: 9595470
    Abstract: Methods for forming tungsten film using fluorine-free tungsten precursors such as tungsten chlorides are provided. Methods involve depositing a tungsten nucleation layer by exposing a substrate to a reducing agent such as diborane (B2H6) and exposing the substrate to a tungsten chloride, followed by depositing bulk tungsten by exposing the substrate to a tungsten chloride and a reducing agent. Methods also involve diluting the reducing agent and exposing the substrate to a fluorine-free precursor in pulses to deposit a tungsten nucleation layer. Deposited films exhibit good step coverage and plugfill.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: March 14, 2017
    Assignee: Lam Research Corporation
    Inventors: Hanna Bamnolker, Raashina Humayun, Juwen Gao, Michal Danek, Joshua Collins
  • Publication number: 20160233220
    Abstract: Disclosed herein are methods and related apparatus for formation of tungsten wordlines in memory devices. Also disclosed herein are methods and related apparatus for deposition of fluorine-free tungsten (FFW). According to various embodiments, the methods involve deposition of multi-component tungsten films using tungsten chloride (WClx) precursors and boron (B)-containing, silicon (Si)-containing or germanium (Ge)-containing reducing agents.
    Type: Application
    Filed: February 10, 2016
    Publication date: August 11, 2016
    Inventors: Michal Danek, Hanna Bamnolker, Raashina Humayun, Juwen Gao
  • Publication number: 20160190008
    Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).
    Type: Application
    Filed: December 10, 2015
    Publication date: June 30, 2016
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Patent number: 9362163
    Abstract: Described are cleaning methods for removing contaminants from an electrical contact interface of a partially fabricated semiconductor substrate. The methods may include introducing a halogen-containing species into a processing chamber, and forming an adsorption-limited layer, which includes halogen from the halogen-containing species, atop the electrical contact interface and/or the contaminants thereon. The methods may further include thereafter removing un-adsorbed halogen-containing species from the processing chamber and activating a reaction between the halogen of the adsorption-limited layer and the contaminants present on the electrical contact interface. The reaction may then result in the removal of at least a portion of the contaminants from the electrical contact interface. In some embodiments, the halogen adsorbed onto the surface and reacted may be fluorine. Also described herein are apparatuses having controllers for implementing such electrical contact interface cleaning techniques.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: June 7, 2016
    Assignee: Lam Research Corporation
    Inventors: Michal Danek, Juwen Gao, Aaron Fellis, Francisco Juarez, Chiukin Steven Lai
  • Publication number: 20160093528
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 31, 2016
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Publication number: 20160071764
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.
    Type: Application
    Filed: February 22, 2013
    Publication date: March 10, 2016
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Patent number: 9240347
    Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: January 19, 2016
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Publication number: 20150325475
    Abstract: Methods for forming tungsten film using fluorine-free tungsten precursors such as tungsten chlorides are provided. Methods involve depositing a tungsten nucleation layer by exposing a substrate to a reducing agent such as diborane (B2H6) and exposing the substrate to a tungsten chloride, followed by depositing bulk tungsten by exposing the substrate to a tungsten chloride and a reducing agent. Methods also involve diluting the reducing agent and exposing the substrate to a fluorine-free precursor in pulses to deposit a tungsten nucleation layer. Deposited films exhibit good step coverage and plugfill.
    Type: Application
    Filed: May 4, 2015
    Publication date: November 12, 2015
    Inventors: Hanna Bamnolker, Raashina Humayun, Juwen Gao, Michal Danek, Joshua Collins
  • Patent number: 9034760
    Abstract: Methods, apparatus, and systems for depositing tensile or compressive tungsten films are described. In one aspect, a method includes providing a substrate to a chamber. The substrate has a field region and a feature recessed from the field region. Then, the substrate is exposed to an organometallic tungsten precursor. The organometallic tungsten precursor not adsorbed onto the substrate is removed from the chamber. The substrate is treated with a first treatment including a heat treatment or a plasma treatment to form a tungsten layer on the substrate. After treating the substrate, residual gasses are removed from the chamber. The tungsten layer on the substrate is treated with a second treatment including a heat treatment or a plasma treatment.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: May 19, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Feng Chen, Tsung-Han Yang, Juwen Gao, Roey Shaviv, Raashina Humayun, Deqi Wang
  • Patent number: 8975184
    Abstract: Methods of filling features with low-resistivity tungsten layers having good fill without use of a nucleation layer are provided. In certain embodiments, the methods involve an optional treatment process prior to chemical vapor deposition of tungsten in the presence of a high partial pressure of hydrogen. According to various embodiments, the treatment process can involve a soaking step or a plasma treatment step. The resulting tungsten layer reduces overall contact resistance in advanced tungsten technology due to elimination of the conventional tungsten nucleation layer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: March 10, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Feng Chen, Tsung-Han Yang, Juwen Gao, Michal Danek