Patents by Inventor Juxiang Ren
Juxiang Ren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9897649Abstract: An integrated circuit facilitates a self test routine that verifies proper operation of an analog comparator. In response to entering the self test routine, the voltage provided to an input of a comparator is changed from being at an operating voltage supply to being at a self test voltage that is used to verify operation of the comparator. In response to the comparator operating properly, the self test voltage provided to the input of the comparator is replaced with the operating voltage supply, and normal operation resumes. The duration of the self test cycle is based upon the amount of time during which the self test voltage is provided to the comparator is asynchronous in nature, and therefore not a function of a clock signal.Type: GrantFiled: September 14, 2015Date of Patent: February 20, 2018Assignee: NXP USA, INC.Inventors: Juxiang Ren, Chris C. Dao, Stefano Pietri
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Publication number: 20170063371Abstract: A substrate bias circuit and method for biasing a substrate are provided. A substrate bias circuit includes a first voltage source, a second voltage source, a diode coupled between the first voltage source and the second voltage source, and a plurality of transistors, each transistor in the plurality of transistors having a substrate terminal. In one example, the first voltage source supplies, via the diode, the substrate terminal of a first transistor of the plurality of transistors during a power-up, and the second voltage source supplies the substrate terminal of the first transistor after the power-up.Type: ApplicationFiled: August 26, 2015Publication date: March 2, 2017Inventors: CHRIS C. DAO, STEFANO PIETRI, JUXIANG REN, ROBERT S. RUTH
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Patent number: 9584118Abstract: A substrate bias circuit and method for biasing a substrate are provided. A substrate bias circuit includes a first voltage source, a second voltage source, a diode coupled between the first voltage source and the second voltage source, and a plurality of transistors, each transistor in the plurality of transistors having a substrate terminal. In one example, the first voltage source supplies, via the diode, the substrate terminal of a first transistor of the plurality of transistors during a power-up, and the second voltage source supplies the substrate terminal of the first transistor after the power-up.Type: GrantFiled: August 26, 2015Date of Patent: February 28, 2017Assignee: NXP USA, INC.Inventors: Chris C. Dao, Stefano Pietri, Juxiang Ren, Robert S. Ruth
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Patent number: 9362904Abstract: A system having a power on reset circuit including a voltage divide), a multiplexer coupled to two outputs of the voltage divider, a first comparator coupled to the multiplexer and a reference, a logic gate coupled to the first comparator, a second comparator coupled to one of the two outputs of the voltage divider, and an emulation gate coupled to the second comparator.Type: GrantFiled: February 28, 2014Date of Patent: June 7, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Chris C. Dao, Stefano Pietri, Juxiang Ren
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Patent number: 9285813Abstract: A supply voltage regulation system for an IC including a temperature sensor that detects temperature of the IC, a scaling resistor coupled between a power grid and a feedback node of the IC, a regulator amplifier that compares a voltage of the feedback node with a reference voltage for developing a supply voltage for the IC, and a temperature scaling circuit that drives a scaling current to the scaling resistor via the feedback node to adjust the supply voltage based on temperature. The temperature scaling circuit may include one or more comparators that compare a temperature signal with corresponding temperature thresholds for selectively applying one or more bias currents to the scaling resistor. The scaling resistor may be coupled to a hot point of the power grid. A voltage difference between a hot point of a ground grid may be converted to a bias current applied to the scaling resistor.Type: GrantFiled: May 20, 2014Date of Patent: March 15, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Stefano Pietri, Juxiang Ren, Chris C. Dao, Anis M. Jarrar
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Publication number: 20160003908Abstract: An integrated circuit facilitates a self test routine that verifies proper operation of an analog comparator. In response to entering the self test routine, the voltage provided to an input of a comparator is changed from being at an operating voltage supply to being at a self test voltage that is used to verify operation of the comparator. In response to the comparator operating properly, the self test voltage provided to the input of the comparator is replaced with the operating voltage supply, and normal operation resumes. The duration of the self test cycle is based upon the amount of time during which the self test voltage is provided to the comparator is asynchronous in nature, and therefore not a function of a clock signal.Type: ApplicationFiled: September 14, 2015Publication date: January 7, 2016Inventors: Juxiang Ren, Chris C. Dao, Stefano Pietri
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Publication number: 20150338864Abstract: A supply voltage regulation system for an IC including a temperature sensor that detects temperature of the IC, a scaling resistor coupled between a power grid and a feedback node of the IC, a regulator amplifier that compares a voltage of the feedback node with a reference voltage for developing a supply voltage for the IC, and a temperature scaling circuit that drives a scaling current to the scaling resistor via the feedback node to adjust the supply voltage based on temperature. The temperature scaling circuit may include one or more comparators that compare a temperature signal with corresponding temperature thresholds for selectively applying one or more bias currents to the scaling resistor. The scaling resistor may be coupled to a hot point of the power grid. A voltage difference between a hot point of a ground grid may be converted to a bias current applied to the scaling resistor.Type: ApplicationFiled: May 20, 2014Publication date: November 26, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: STEFANO PIETRI, JUXIANG REN, CHRIS C. DAO, ANIS M. JARRAR
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Patent number: 9134395Abstract: An integrated circuit facilitates a self test routine that verifies proper operation of an analog comparator. In response to entering the self test routine, the voltage provided to an input of a comparator is changed from being at an operating voltage supply to being at a self test voltage that is used to verify operation of the comparator. In response to the comparator operating properly, the self test voltage provided to the input of the comparator is replaced with the operating voltage supply, and normal operation resumes. The duration of the self test cycle is based upon the amount of time during which the self test voltage is provided to the comparator is asynchronous in nature, and therefore not a function of a clock signal.Type: GrantFiled: March 7, 2012Date of Patent: September 15, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Juxiang Ren, Chris C. Dao, Stefano Pietri
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Publication number: 20150247893Abstract: A system having a power on reset circuit including a voltage divide), a multiplexer coupled to two outputs of the voltage divider, a first comparator coupled to the multiplexer and a reference, a logic gate coupled to the first comparator, a second comparator coupled to one of the two outputs of the voltage divider, and an emulation gate coupled to the second comparator.Type: ApplicationFiled: February 28, 2014Publication date: September 3, 2015Inventors: CHRIS C. DAO, STEFANO PIETRI, JUXIANG REN
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Patent number: 9041367Abstract: A voltage regulator includes an amplifier having a first input coupled to a first reference voltage and a second input coupled to a voltage feedback signal; a multiplexer having a first input coupled to an output of the amplifier, a second input coupled to a voltage clamp signal, and a control input; and a control circuit having a first input coupled to an over current indicator, a second input coupled to a no over voltage indicator, a third input coupled to a timer signal, and an output coupled to the control input of the multiplexer.Type: GrantFiled: March 14, 2013Date of Patent: May 26, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Chris C. Dao, Stefano Pietri, Juxiang Ren
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Patent number: 8994446Abstract: An integrated circuit includes a device of a first conductivity type formed in a first well; a voltage regulator configured to provide a bias voltage to the first well based on a first reference voltage which is generated using a first band gap reference generator; and a monitor circuit configured to compare a voltage of the first well to an upper limit and a lower limit of a first voltage range, wherein each of the upper limit and lower limit is provided using a second band gap reference generator, separate from the first band gap reference generator, wherein, in response to determining that the voltage of the first well is outside of the first voltage range, providing a first out of range indicator.Type: GrantFiled: June 28, 2013Date of Patent: March 31, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Stefano Pietri, Chris C. Dao, Anis M. Jarrar, Juxiang Ren
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Publication number: 20150002215Abstract: An integrated circuit includes a device of a first conductivity type formed in a first well; a voltage regulator configured to provide a bias voltage to the first well based on a first reference voltage which is generated using a first band gap reference generator; and a monitor circuit configured to compare a voltage of the first well to an upper limit and a lower limit of a first voltage range, wherein each of the upper limit and lower limit is provided using a second band gap reference generator, separate from the first band gap reference generator, wherein, in response to determining that the voltage of the first well is outside of the first voltage range, providing a first out of range indicator.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: Stefano Pietri, Chris C. Dao, Anis M. Jarrar, Juxiang Ren
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Patent number: 8896370Abstract: A voltage regulator bypass circuit to control bypass of a voltage regulator of an integrated circuit device, the voltage regulator bypass circuit including a first voltage detector, a second voltage detector, and circuit. The first voltage detector to detect that a core circuitry voltage level is above a first threshold and to assert a first detect signal at an output in response to the detection. The second voltage detector to detect that an unregulated supply voltage is above a second threshold and to assert a second detect signal at an output in response to the detection. The circuit having a first input coupled to the output of the first voltage detector and a second input coupled to the output of the second voltage detector, the circuit to bypass the voltage regulator in response the output of the latch being cleared.Type: GrantFiled: December 13, 2013Date of Patent: November 25, 2014Assignees: Freescale Semiconductor, Inc., STMicroelectronics SRL, STMicroelectronics Private Ltd.Inventors: Stefano Pietri, Chris C. Dao, Juxiang Ren, Nicolas Grossier, V Srinivasan
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Publication number: 20140266098Abstract: A voltage regulator includes an amplifier having a first input coupled to a first reference voltage and a second input coupled to a voltage feedback signal; a multiplexer having a first input coupled to an output of the amplifier, a second input coupled to a voltage clamp signal, and a control input; and a control circuit having a first input coupled to an over current indicator, a second input coupled to a no over voltage indicator, a third input coupled to a timer signal, and an output coupled to the control input of the multiplexer.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Inventors: Chris C. Dao, Stefano Pietri, Juxiang Ren
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Publication number: 20140264728Abstract: A semiconductor device includes CMP dummy tiles (36) that are converted to active tiles by forming well regions (42) at a top surface of the dummy tiles, forming silicide (52) on top of the well regions, and forming, a metal interconnect structure (72, 82) in contact with the silicided well tie regions for electrically connecting the dummy tiles to a predetermined supply voltage to provide latch-up protection.Type: ApplicationFiled: May 29, 2014Publication date: September 18, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Robert S. Ruth, Mark A. Kearney, Bernard J. Pappert, Juxiang Ren, Jeff L. Warner
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Publication number: 20140203794Abstract: A bandgap reference system has a bandgap circuit, an operational transconductance amplifier, and an offset controller. The bandgap circuit includes a pair of diode devices and has a reference terminal at which is provided a bandgap reference voltage. The bandgap circuit provides a differential output having a first output and a second output. The operational transconductance amplifier has a first input coupled to the first output of the bandgap circuit, a second input coupled to the second output of the bandgap reference circuit, and an output coupled to the reference terminal. The offset controller is coupled to the operational transconductance amplifier and to the first and second outputs of the bandgap circuit. The offset controller trims the operational transconductance amplifier as needed to ensure an offset of the operational transconductance amplifier is below a predetermined level.Type: ApplicationFiled: January 24, 2013Publication date: July 24, 2014Inventors: STEFANO PIETRI, Chris C. Dao, Juxiang Ren
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Patent number: 8765607Abstract: A semiconductor device includes CMP dummy tiles (36) that are converted to active tiles by forming well regions (42) at a top surface of the dummy tiles, forming silicide (52) on top of the well regions, and forming a metal interconnect structure (72, 82) in contact with the silicided well tie regions for electrically connecting the dummy tiles to a predetermined supply voltage to provide latch-up protection.Type: GrantFiled: June 1, 2011Date of Patent: July 1, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Robert S. Ruth, Mark A. Kearney, Bernard J. Pappert, Juxiang Ren, Jeff L. Warner
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Publication number: 20140118036Abstract: A voltage regulator bypass circuit to control bypass of a voltage regulator of an integrated circuit device, the voltage regulator bypass circuit including a first voltage detector, a second voltage detector, and circuit. The first voltage detector to detect that a core circuitry voltage level is above a first threshold and to assert a first detect signal at an output in response to the detection. The second voltage detector to detect that an unregulated supply voltage is above a second threshold and to assert a second detect signal at an output in response to the detection. The circuit having a first input coupled to the output of the first voltage detector and a second input coupled to the output of the second voltage detector, the circuit to bypass the voltage regulator in response the output of the latch being cleared.Type: ApplicationFiled: December 13, 2013Publication date: May 1, 2014Applicants: FREESCALE SEMICONDUCTOR, INC., STMICROELECTRONICS PRIVATE LTD., STMICROELECTRONICS SRLInventors: Stefano Pietri, Chris C. Dao, Juxiang Ren, Nicolas Grossier, V. Srinivasan
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Patent number: 8629713Abstract: A voltage regulator bypass circuit to control bypass of a voltage regulator of an integrated circuit device, the voltage regulator bypass circuit including a first voltage detector, a second voltage detector, and circuit. The first voltage detector to detect that a core circuitry voltage level is above a first threshold and to assert a first detect signal at an output in response to the detection. The second voltage detector to detect that an unregulated supply voltage is above a second threshold and to assert a second detect signal at an output in response to the detection. The circuit having a first input coupled to the output of the first voltage detector and a second input coupled to the output of the second voltage detector, the circuit to bypass the voltage regulator in response the output of the latch being cleared.Type: GrantFiled: May 29, 2012Date of Patent: January 14, 2014Assignees: Freescale Semiconductor, Inc., STMicroelectronics SRL, STMicroelectronics Private Ltd.Inventors: Stefano Pietri, Chris C. Dao, Juxiang Ren, Nicolas Grosssier, V Srinivasan
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Publication number: 20130321071Abstract: A voltage regulator bypass circuit to control bypass of a voltage regulator of an integrated circuit device, the voltage regulator bypass circuit including a first voltage detector, a second voltage detector, and circuit. The first voltage detector to detect that a core circuitry voltage level is above a first threshold and to assert a first detect signal at an output in response to the detection. The second voltage detector to detect that an unregulated supply voltage is above a second threshold and to assert a second detect signal at an output in response to the detection. The circuit having a first input coupled to the output of the first voltage detector and a second input coupled to the output of the second voltage detector, the circuit to bypass the voltage regulator in response the output of the latch being cleared.Type: ApplicationFiled: May 29, 2012Publication date: December 5, 2013Applicants: FREESCALE SEMICONDUCTOR, INC., STMICROELECTRONICS PRIVATE LTD., STMICROELECTRONICS SRLInventors: Stefano Pietri, Chris C. Dao, Juxiang Ren, Nicolas Grossier, V. Srinivasan