Abstract: The present invention relates to a three-dimensional structure electrode, a method for manufacturing same, and an electrochemical element including the electrode. The present invention is characterized by comprising: (a) an upper conductive layer and a lower conductive layer which have a structure constituting an assembly within which a conductive material and a porous nonwoven fabric including a plurality of polymeric fibers are three-dimensionally connected in an irregular and continuous manner, thereby forming a mutually connected porous structure; and (b) an active material layer forming the same assembly structure as the conductive layers and forming a three-dimensionally filled structure in which electrode active material particles are uniformly filled inside the mutually connected porous structure formed in the assembly structure, wherein the active material layer is formed between the upper conductive layer and the lower conductive layer.

Abstract: A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.

Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

Abstract: A gripper includes a body part, a finger base part coupled to the body part, and a finger part coupled to a first side of the body part or the finger base part and coupled to the body part or the finger base part to be reciprocal, wherein the finger part comprises a first link structure and a second link structure, sides of which are coupled to the finger base part, respectively, and wherein, in the first link structure and the second link structure, a first support area of the first link structure and a second support area of the second link structure reciprocate in only one of a plurality of directions that cross a direction in which the finger part reciprocates with respect to the finger base part.

Abstract: A gripper includes a body part, a finger base part coupled to the body part to be rotatable, the finger base part including a first finger base part and a second finger base part configured such that when the first finger base part is rotated in a first direction with respect to the body part, the second finger base part is provided to be rotatable in a second direction opposite the first direction with respect to the body part, and a finger part coupled to a first side of the body part or the finger base part to be reciprocal.

Abstract: An embodiment device includes an input module including a motor configured to generate a rotational force, an output module configured to receive power from the input module to be rotatable, and a connection module having a first side coupled to the input module and a second side, opposite the first side, coupled to the output module, wherein the connection module is configured to transmit the power from the input module to the output module.

Abstract: A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.

Abstract: A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.

Abstract: A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.

Abstract: A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.

Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, the electrodes including pad portions on the connection region, respectively, and the pad portions of the electrodes being stacked in a staircase structure, first vertical structures penetrating the electrode structure on the cell array region, and second vertical structures penetrating the electrode structure on the connection region, each of the second vertical structures including first parts spaced apart from each other in a first direction, and at least one second part connecting the first parts to each other, the at least one second part penetrating sidewalls of the pad portions, respectively.

Abstract: A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.

Abstract: A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.

Abstract: The present invention relates to a cooling device for preventing fire due to spontaneous combustion of coal stockpiles in a coal-fired power plant, and more specifically, to a cooling device for preventing spontaneous combustion of coal stockpiles, for which a plurality of cooling devices are provided at a predetermined interval in coal stockpiles and, when a temperature (ignition temperature) specified by a user is detected from the outer surface, compressed liquefied nitrogen stored in the cooling device is ejected to lower a temperature around the loaded coal, thereby preventing spontaneous combustion by the oxidation of coal.

Abstract: A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.

Abstract: The present invention relates to a cooling device for preventing fire due to spontaneous combustion of coal stockpiles in a coal-fired power plant, and more specifically, to a cooling device for preventing spontaneous combustion of coal stockpiles, for which a plurality of cooling devices are provided at a predetermined interval in coal stockpiles and, when a temperature (ignition temperature) specified by a user is detected from the outer surface, compressed liquefied nitrogen stored in the cooling device is ejected to lower a temperature around the loaded coal, thereby preventing spontaneous combustion by the oxidation of coal.