Patents by Inventor Jyh-Cherng Sheu
Jyh-Cherng Sheu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20180247935Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.Type: ApplicationFiled: April 20, 2018Publication date: August 30, 2018Inventors: Chih-Yu Hsu, Yi-Tang Lin, Clement Hsingjen Wann, Chih-Sheng Chang, Wei-Chun Tsai, Jyh-Cherng Sheu, Chi-Yuan Shih
-
Publication number: 20180151683Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.Type: ApplicationFiled: January 30, 2017Publication date: May 31, 2018Inventors: Yee-Chia YEO, Hung-Li CHIANG, Jyh-Cherng SHEU, Sung-Li WANG, I-Sheng CHEN, Chi On CHUI
-
Patent number: 9953975Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.Type: GrantFiled: July 19, 2013Date of Patent: April 24, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Yu Hsu, Yi-Tang Lin, Clement Hsinjen Wann, Chih-Sheng Chang, Wei-Chun Tsai, Jyh-Cherng Sheu, Chi-Yuan Shih
-
Publication number: 20180102436Abstract: A semiconductor device includes a substrate, a fin structure disposed over the substrate and including a channel region and a source/drain region, a gate structure disposed over at least a portion of the fin structure, the channel region being beneath the gate structure and the source/drain region being outside of the gate structure, a strain material layer disposed over the source/drain region, the strain material layer providing stress to the first channel region, and a contact layer wrapping around the first strain material layer. A width of the source/drain region is smaller than a width of the channel region.Type: ApplicationFiled: December 11, 2017Publication date: April 12, 2018Inventors: Hung-Li CHIANG, Cheng-Yi PENG, Jyh-Cherng SHEU, Yee-Chia YEO
-
Patent number: 9899258Abstract: Overhang reduction methods are disclosed. In some embodiments, a method includes forming a recess in a dielectric layer, the recess defining first sidewalls of the dielectric layer. The method also includes depositing a first conductive layer over an upper surface of the dielectric layer and the sidewalls of the dielectric layer, the first conductive layer having a first overhang, removing the first overhang of the first conductive layer using an etchant selected from the group consisting of a halide of the first conductive layer, Cl2, BCl3, SPM, SC1, SC2, and combinations thereof, and filling the recess with a second conductive layer.Type: GrantFiled: September 30, 2016Date of Patent: February 20, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Wen Wu, Sung-Li Wang, Min-Hsiu Hung, Yida Li, Chih-Wei Chang, Huang-Yi Huang, Cheng-Tung Lin, Jyh-Cherng Sheu, Yee-Chia Yeo, Chi On Chui
-
Publication number: 20180033687Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer to expose a conductive element. The method also includes forming a conductive layer over the conductive element and modifying an upper portion of the conductive layer using a plasma operation to form a modified region. The method further includes forming a conductive plug over the modified region.Type: ApplicationFiled: July 29, 2016Publication date: February 1, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Min-Hsiu HUNG, Sung-Li WANG, Pei-Wen WU, Yida LI, Chih-Wei CHANG, Huang-Yi HUANG, Cheng-Tung LIN, Jyh-Cherng SHEU, Yee-Chia YEO, Chi-On CHUI
-
Patent number: 9859427Abstract: A semiconductor device includes a substrate, a fin structure disposed over the substrate and including a channel region and a source/drain region, a gate structure disposed over at least a portion of the fin structure, the channel region being beneath the gate structure and the source/drain region being outside of the gate structure, a strain material layer disposed over the source/drain region, the strain material layer providing stress to the first channel region, and a contact layer wrapping around the first strain material layer. A width of the source/drain region is smaller than a width of the channel region.Type: GrantFiled: September 29, 2016Date of Patent: January 2, 2018Assignee: Tawain Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Li Chiang, Cheng-Yi Peng, Jyh-Cherng Sheu, Yee-Chia Yeo
-
Publication number: 20170207095Abstract: In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material.Type: ApplicationFiled: January 14, 2016Publication date: July 20, 2017Inventors: Kai-Hsuan LEE, Jyh-Cherng SHEU, Sung-Li WANG, Cheng-Yu YANG, Sheng-Chen WANG, Sai-Hooi YEONG
-
Patent number: 9698030Abstract: A temperature controlled loadlock chamber for use in semiconductor processing is provided. The temperature controlled loadlock chamber may include one or more of an adjustable fluid pump, mass flow controller, one or more temperature sensors, and a controller. The adjustable fluid pump provides fluid having a predetermined temperature to a temperature-controlled plate. The mass flow controller provides gas flow into the chamber that may also aid in maintaining a desired temperature. Additionally, one or more temperature sensors may be combined with the adjustable fluid pump and/or the mass flow controller to provide feedback and to provide a greater control over the temperature. A controller may be added to control the adjustable fluid pump and the mass flow controller based upon temperature readings from the one or more temperature sensors.Type: GrantFiled: November 10, 2014Date of Patent: July 4, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hsien Lin, Jyh-Cherng Sheu, Ming-Feng Yoo, Kewei Zuo
-
Publication number: 20170069756Abstract: A semiconductor device includes a substrate, a fin structure disposed over the substrate and including a channel region and a source/drain region, a gate structure disposed over at least a portion of the fin structure, the channel region being beneath the gate structure and the source/drain region being outside of the gate structure, a strain material layer disposed over the source/drain region, the strain material layer providing stress to the first channel region, and a contact layer wrapping around the first strain material layer. A width of the source/drain region is smaller than a width of the channel region.Type: ApplicationFiled: September 29, 2016Publication date: March 9, 2017Inventors: Hung-Li CHIANG, Cheng-Yi PENG, Jyh-Cherng SHEU, Yee-Chia YEO
-
Patent number: 9472669Abstract: In a method of fabricating a Fin FET, first and second fin structures are formed. The first and second fin structures protrude from an isolation insulating layer. A gate structure is formed over the first and second fin structures, each of which has source/drain regions, having a first width, outside of the gate structure. Portions of sidewalls of the source/drain regions are removed to form trimmed source/drain regions, each of which has a second width smaller than the first width. A strain material is formed over the trimmed source/drain regions such that the strain material formed on the first fin structure is separated from that on the second fin structure. An interlayer dielectric layer is formed over the gate structure and the source/drain regions with the strain material. A contact layer is formed on the strain material such that the contact layer wraps around the strain material.Type: GrantFiled: September 4, 2015Date of Patent: October 18, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Li Chiang, Cheng-Yi Peng, Jyh-Cherng Sheu, Yee-Chia Yeo
-
Publication number: 20150132100Abstract: A temperature controlled loadlock chamber for use in semiconductor processing is provided. The temperature controlled loadlock chamber may include one or more of an adjustable fluid pump, mass flow controller, one or more temperature sensors, and a controller. The adjustable fluid pump provides fluid having a predetermined temperature to a temperature-controlled plate. The mass flow controller provides gas flow into the chamber that may also aid in maintaining a desired temperature. Additionally, one or more temperature sensors may be combined with the adjustable fluid pump and/or the mass flow controller to provide feedback and to provide a greater control over the temperature. A controller may be added to control the adjustable fluid pump and the mass flow controller based upon temperature readings from the one or more temperature sensors.Type: ApplicationFiled: November 10, 2014Publication date: May 14, 2015Inventors: Chun-Hsien Lin, Jyh-Cherng Sheu, Ming-Feng Yoo, Kewei Zuo
-
Publication number: 20150021710Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.Type: ApplicationFiled: July 19, 2013Publication date: January 22, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Yu Hsu, Yi-Tang Lin, Clement Hsinjen Wann, Chih-Sheng Chang, Wei-Chun Tsai, Jyh-Cherng Sheu, Chi-Yuan Shih
-
Patent number: 8905124Abstract: A temperature controlled loadlock chamber for use in semiconductor processing is provided. The temperature controlled loadlock chamber may include one or more of an adjustable fluid pump, mass flow controller, one or more temperature sensors, and a controller. The adjustable fluid pump provides fluid having a predetermined temperature to a temperature-controlled plate. The mass flow controller provides gas flow into the chamber that may also aid in maintaining a desired temperature. Additionally, one or more temperature sensors may be combined with the adjustable fluid pump and/or the mass flow controller to provide feedback and to provide a greater control over the temperature. A controller may be added to control the adjustable fluid pump and the mass flow controller based upon temperature readings from the one or more temperature sensors.Type: GrantFiled: June 27, 2007Date of Patent: December 9, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hsien Lin, Jyh-Cherng Sheu, Ming-Feng Yoo, Kewei Zuo
-
Patent number: 8860208Abstract: An integrated circuit structure includes a first chip including a first edge; and a second chip having a second edge facing the first edge. A scribe line is between and adjoining the first edge and the second edge. A heat spreader includes a portion in the scribe line, wherein the heat spreader includes a plurality of vias and a plurality of metal lines. The portion of the heat spreader in the scribe line has a second length at least close to, or greater than, a first length of the first edge.Type: GrantFiled: February 8, 2011Date of Patent: October 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Yu-Wen Liu, Jyh-Cherng Sheu, Hao-Yi Tsai, Shin-Puu Jeng, Chen-Hua Yu, Shang-Yun Hou
-
Patent number: 8822293Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate, wherein the semiconductor substrate and a sidewall of the gate dielectric has a joint point; forming a gate electrode over the gate dielectric; forming a mask layer over the semiconductor substrate and the gate electrode, wherein a first portion of the mask layer adjacent the joint point is at least thinner than a second portion of the mask layer away from the joint point; after the step of forming the mask layer, performing a halo/pocket implantation to introduce a halo/pocket impurity into the semiconductor substrate; and removing the mask layer after the halo/pocket implantation.Type: GrantFiled: March 13, 2008Date of Patent: September 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Yihang Chiu, Shu-Tine Yang, Jyh-Cherng Sheu, Chu-Yun Fu, Cheng-Tung Lin
-
Patent number: 8795486Abstract: A PVD target structure for use in physical vapor deposition. The PVD target structure includes a consumable slab of source material and one or more detectors for indicating when the slab of source material is approaching or has been reduced to a given quantity representing a service lifetime endpoint of the target structure.Type: GrantFiled: June 29, 2006Date of Patent: August 5, 2014Assignee: Taiwan semiconductor Manufacturing Company, Ltd.Inventors: Yi-Li Hsiao, Jerry Hwang, Jyh-Cherng Sheu, Lawrance Sheu, Jean Wang, Chen-Hua Yu
-
Publication number: 20130260056Abstract: Apparatuses and processes for maskless deposition of electronic and biological materials. The process is capable of direct deposition of features with linewidths varying from the micron range up to a fraction of a millimeter, and may be used to deposit features on substrates with damage thresholds near 100° C. Deposition and subsequent processing may be carried out under ambient conditions, eliminating the need for a vacuum atmosphere. The process may also be performed in an inert gas environment. Deposition of and subsequent laser post processing produces linewidths as low as 1 micron, with sub-micron edge definition. The apparatus nozzle has a large working distance—the orifice to substrate distance may be several millimeters—and direct write onto non-planar surfaces is possible.Type: ApplicationFiled: June 4, 2013Publication date: October 3, 2013Inventors: Michael J. Renn, Bruce H. King, Marcelino Essien, Gregory J. Marquez, Manampathy G. Giridharan, Jyh-Cherng Sheu
-
Patent number: 8455051Abstract: Apparatuses and processes for maskless deposition of electronic and biological materials. The process is capable of direct deposition of features with linewidths varying from the micron range up to a fraction of a millimeter, and may be used to deposit features on substrates with damage thresholds near 100° C. Deposition and subsequent processing may be carried out under ambient conditions, eliminating the need for a vacuum atmosphere. The process may also be performed in an inert gas environment. Deposition of and subsequent laser post processing produces linewidths as low as 1 micron, with sub-micron edge definition. The apparatus nozzle has a large working distance—the orifice to substrate distance may be several millimeters—and direct write onto non-planar surfaces is possible.Type: GrantFiled: December 22, 2010Date of Patent: June 4, 2013Assignee: Optomec, Inc.Inventors: Michael J. Renn, Bruce H. King, Marcelino Essien, Gregory J. Marquez, Manampathy G. Giridharan, Jyh-Cherng Sheu
-
Patent number: 8110247Abstract: A method of depositing various materials onto heat-sensitive targets, particularly oxygen-sensitive materials. Heat-sensitive targets are generally defined as targets that have thermal damage thresholds that are lower than the temperature required to process a deposited material. The invention uses precursor solutions and/or particle or colloidal suspensions, along with optional pre-deposition treatment and/or post-deposition treatment to lower the laser power required to drive the deposit to its final state. The present invention uses Maskless Mesoscale Material Deposition (M3D™) to perform direct deposition of material onto the target in a precise, highly localized fashion. Features with linewidths as small as 4 microns may be deposited, with little or no material waste. A laser is preferably used to heat the material to process it to obtain the desired state, for example by chemical decomposition, sintering, polymerization, and the like.Type: GrantFiled: May 8, 2006Date of Patent: February 7, 2012Assignee: Optomec Design CompanyInventors: Michael J. Renn, Bruce H. King, Marcelino Essien, Manampathy G. Giridharan, Jyh-Cherng Sheu