Patents by Inventor Jyh-Kang Ting
Jyh-Kang Ting has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11281835Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.Type: GrantFiled: April 28, 2020Date of Patent: March 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
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Patent number: 10998304Abstract: A conductive line structure includes two conductive lines in a layout. The two cut lines are over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.Type: GrantFiled: April 22, 2019Date of Patent: May 4, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
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Publication number: 20200257842Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.Type: ApplicationFiled: April 28, 2020Publication date: August 13, 2020Inventors: Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
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Patent number: 10664639Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.Type: GrantFiled: May 4, 2018Date of Patent: May 26, 2020Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
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Publication number: 20190244950Abstract: A conductive line structure includes two conductive lines in a layout. The two cut lines are over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.Type: ApplicationFiled: April 22, 2019Publication date: August 8, 2019Inventors: Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
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Patent number: 10283495Abstract: A semiconductor device includes two elongated active regions that include source/drain regions for multiple transistor devices, a first contact layer that includes an electrical connection between the two active regions, a second contact layer that includes a connection between two gate lines, and a gate contact layer that provides connections to the gate lines.Type: GrantFiled: April 1, 2016Date of Patent: May 7, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ru-Gun Liu, Chun-Yi Lee, Jyh-Kang Ting, Juing-Yi Wu, Liang-Yao Lee, Tung-Heng Hsieh, Tsung-Chieh Tsai
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Patent number: 10269785Abstract: A conductive line structure includes two conductive lines in a layout. The two cut lines are over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.Type: GrantFiled: September 30, 2016Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
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Publication number: 20180253522Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.Type: ApplicationFiled: May 4, 2018Publication date: September 6, 2018Inventors: Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
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Patent number: 9984191Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.Type: GrantFiled: August 29, 2014Date of Patent: May 29, 2018Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
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Patent number: 9746783Abstract: A method for ameliorating corner rounding effects in a photolithographic process is provided. A semiconductor workpiece having an active device region is provided, and a photoresist layer is formed over the semiconductor workpiece. A mask is provided for patterning for the photoresist layer, wherein the mask comprises pattern having a sharp corner associated with the active device region. The sharp corner is separated from the active device region by a first distance in a first direction and a second distance in a second direction, wherein the first distance meets a minimum criteria for the photolithographic process, and wherein the second distance is greater than the first distance. The photoresist layer is then exposed to a radiation source, and the radiation source patterns the photoresist layer through the mask, defining an exposure region on the semiconductor workpiece having a rounded corner associated with the sharp corner.Type: GrantFiled: August 15, 2013Date of Patent: August 29, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Liang-Yao Lee, Jyh-Kang Ting, Tsung-Chieh Tsai, Juing-Yi Wu
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Patent number: 9637818Abstract: Among other things, one or more systems and techniques for defining one or more implant regions or for doping a semiconductor arrangement are provided. A first implant region is defined based upon a first implant mask overlaying a first active region of a semiconductor arrangement. A second implant region is defined based upon the first implant mask and a second implant mask overlaying a second active region of the semiconductor arrangement. A third implant region is defined based upon the second implant mask overlaying a third active region of the semiconductor arrangement. One or more doping processes are performed through the first implant mask and the second implant mask to dope the semiconductor arrangement. Because the first implant mask and the second implant mask overlap the second active region, doping area coverage is improved thus mitigating undesirable voltage threshold variations otherwise resulting from inadequate doping area coverage.Type: GrantFiled: July 20, 2015Date of Patent: May 2, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Juing-Yi Wu, Jyh-Kang Ting, Tsung-Chieh Tsai, Liang-Yao Lee
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Patent number: 9620420Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal connect over and connected to a first active region, over and connected to a second active region and over a shallow trench isolation (STI) region thereby connecting the first active region to the second active region. A metal contact is over and connected to a gate in the STI region. The metal connect is formed in a first opening and the metal contact is formed in a second opening, where the first opening and the second opening are formed concurrently using a single mask. The semiconductor arrangement formed using a single mask is less expensive to fabricate and requires fewer etching operations than a semiconductor arrangement formed using multiple masks.Type: GrantFiled: May 20, 2016Date of Patent: April 11, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chen-Hung Lu, Chie-luan Lin, Ming-Yi Lin, Yen-Sen Wang, Jyh-Kang Ting
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Publication number: 20170025401Abstract: A conductive line structure includes two conductive lines in a layout. The two cut lines are over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.Type: ApplicationFiled: September 30, 2016Publication date: January 26, 2017Inventors: Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
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Patent number: 9551923Abstract: Some embodiments relate to a method of designing an integrated circuit layout. In this method, a plurality of design shapes are provided on different design layers over an active area within a graphical representation of the layout. A connection extends perpendicularly between a first design shape formed on a first design layer and a second design shape formed on the first design layer. First and second cut mask shapes on first and second cut mask design layers, respectively, are generated. The first cut shape removes portions of the first design layer and the second cut shape removes portions of the second design layer.Type: GrantFiled: April 8, 2014Date of Patent: January 24, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Sen Wang, Ming-Yi Lin, Chen-Hung Lu, Jyh-Kang Ting
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Patent number: 9508791Abstract: A semiconductor device comprises a non-conductive gate feature over a substrate, and a metal gate electrode over the substrate. The metal gate electrode comprises a portion over an active region of the substrate, and a portion over an isolation feature of the substrate ending at an end cap. A vertical profile of the metal gate electrode at the end cap matches a vertical profile of the metal gate electrode in the portion over the active region.Type: GrantFiled: January 7, 2016Date of Patent: November 29, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Chieh Tsai, Yung-Che Albert Shih, Jyh-Kang Ting, Juing-Yi Wu, Liang-Yao Lee
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Patent number: 9472501Abstract: A conductive line structure includes two conductive lines in a layout. The two cut lines are over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.Type: GrantFiled: July 28, 2015Date of Patent: October 18, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
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Publication number: 20160293590Abstract: A semiconductor device includes two elongated active regions that include source/drain regions for multiple transistor devices, a first contact layer that includes an electrical connection between the two active regions, a second contact layer that includes a connection between two gate lines, and a gate contact layer that provides connections to the gate lines.Type: ApplicationFiled: April 1, 2016Publication date: October 6, 2016Inventors: Ru-Gun Liu, Chun-Yi Lee, Jyh-Kang Ting, Juing-Yi Wu, Liang-Yao Lee, Tung-Heng Hsieh, Tsung-Chieh Tsai
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Publication number: 20160268170Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal connect over and connected to a first active region, over and connected to a second active region and over a shallow trench isolation (STI) region thereby connecting the first active region to the second active region. A metal contact is over and connected to a gate in the STI region. The metal connect is formed in a first opening and the metal contact is formed in a second opening, where the first opening and the second opening are formed concurrently using a single mask. The semiconductor arrangement formed using a single mask is less expensive to fabricate and requires fewer etching operations than a semiconductor arrangement formed using multiple masks.Type: ApplicationFiled: May 20, 2016Publication date: September 15, 2016Inventors: Chen-Hung Lu, Chie-luan Lin, Ming-Yi Lin, Yen-Sen Wang, Jyh-Kang Ting
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Patent number: 9391056Abstract: A method for mask optimization, the method including moving any features of a gate contact mask that are in violation of a spacing rule to a second layer contact mask, splitting an elongated feature of the second layer mask that is too close to a feature moved to the second layer mask from the gate contact mask, and connecting two split features of a first layer contact mask, the split features corresponding to the elongated feature of the second layer mask.Type: GrantFiled: August 16, 2013Date of Patent: July 12, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting, Chun-Yi Lee
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Patent number: 9349634Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal connect over and connected to a first active region, over and connected to a second active region and over a shallow trench isolation (STI) region thereby connecting the first active region to the second active region. A metal contact is over and connected to a gate in the STI region. The metal connect is formed in a first opening and the metal contact is formed in a second opening, where the first opening and the second opening are formed concurrently using a single mask. The semiconductor arrangement formed using a single mask is less expensive to fabricate and requires fewer etching operations than a semiconductor arrangement formed using multiple masks.Type: GrantFiled: February 21, 2014Date of Patent: May 24, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chen-Hung Lu, Chie-Iuan Lin, Yen-Sen Wang, Ming-Yi Lin, Jyh-Kang Ting