Patents by Inventor Jyh-Kang Ting
Jyh-Kang Ting has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160133693Abstract: A semiconductor device comprises a non-conductive gate feature over a substrate, and a metal gate electrode over the substrate. The metal gate electrode comprises a portion over an active region of the substrate, and a portion over an isolation feature of the substrate ending at an end cap. A vertical profile of the metal gate electrode at the end cap matches a vertical profile of the metal gate electrode in the portion over the active region.Type: ApplicationFiled: January 7, 2016Publication date: May 12, 2016Inventors: Tsung-Chieh Tsai, Yung-Che Albert Shih, Jyh-Kang Ting, Juing-Yi Wu, Liang-Yao Lee
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Publication number: 20160063166Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.Type: ApplicationFiled: August 29, 2014Publication date: March 3, 2016Inventors: Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
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Publication number: 20150333002Abstract: A conductive line structure includes two conductive lines in a layout. The two cut lines are over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.Type: ApplicationFiled: July 28, 2015Publication date: November 19, 2015Inventors: Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
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Publication number: 20150322565Abstract: Among other things, one or more systems and techniques for defining one or more implant regions or for doping a semiconductor arrangement are provided. A first implant region is defined based upon a first implant mask overlaying a first active region of a semiconductor arrangement. A second implant region is defined based upon the first implant mask and a second implant mask overlaying a second active region of the semiconductor arrangement. A third implant region is defined based upon the second implant mask overlaying a third active region of the semiconductor arrangement. One or more doping processes are performed through the first implant mask and the second implant mask to dope the semiconductor arrangement. Because the first implant mask and the second implant mask overlap the second active region, doping area coverage is improved thus mitigating undesirable voltage threshold variations otherwise resulting from inadequate doping area coverage.Type: ApplicationFiled: July 20, 2015Publication date: November 12, 2015Inventors: Juing-Yi Wu, Jyh-Kang Ting, Tsung-Chieh Tsai, Liang-Yao Lee
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Publication number: 20150286765Abstract: Some embodiments relate to a method of designing an integrated circuit layout. In this method, a plurality of design shapes are provided on different design layers over an active area within a graphical representation of the layout. A connection extends perpendicularly between a first design shape formed on a first design layer and a second design shape formed on the first design layer. First and second cut mask shapes on first and second cut mask design layers, respectively, are generated. The first cut shape removes portions of the first design layer and the second cut shape removes portions of the second design layer.Type: ApplicationFiled: April 8, 2014Publication date: October 8, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Sen Wang, Ming-Yi Lin, Chen-Hung Lu, Jyh-Kang Ting
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Patent number: 9136168Abstract: A method includes placing two conductive lines in a layout. Two cut lines are placed over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.Type: GrantFiled: June 28, 2013Date of Patent: September 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
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Publication number: 20150243552Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal connect over and connected to a first active region, over and connected to a second active region and over a shallow trench isolation (STI) region thereby connecting the first active region to the second active region. A metal contact is over and connected to a gate in the STI region. The metal connect is formed in a first opening and the metal contact is formed in a second opening, where the first opening and the second opening are formed concurrently using a single mask. The semiconductor arrangement formed using a single mask is less expensive to fabricate and requires fewer etching operations than a semiconductor arrangement formed using multiple masks.Type: ApplicationFiled: February 21, 2014Publication date: August 27, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chen-Hung Lu, Chie-Iuan Lin, Yen-Sen Wang, Ming-Yi Lin, Jyh-Kang Ting
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Patent number: 9087773Abstract: Among other things, one or more systems and techniques for defining one or more implant regions or for doping a semiconductor arrangement are provided. A first implant region is defined based upon a first implant mask overlaying a first active region of a semiconductor arrangement. A second implant region is defined based upon the first implant mask and a second implant mask overlaying a second active region of the semiconductor arrangement. A third implant region is defined based upon the second implant mask overlaying a third active region of the semiconductor arrangement. One or more doping processes are performed through the first implant mask and the second implant mask to dope the semiconductor arrangement. Because the first implant mask and the second implant mask overlap the second active region, doping area coverage is improved thus mitigating undesirable voltage threshold variations otherwise resulting from inadequate doping area coverage.Type: GrantFiled: September 11, 2013Date of Patent: July 21, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Juing-Yi Wu, Jyh-Kang Ting, Tsung-Chieh Tsai, Liang-Yao Lee
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Patent number: 9047437Abstract: Provided is a system and method for designing the layout of integrated circuits or other semiconductor devices while directly accessing design rules and a library of design features by interfacing with a GUI upon which the design layout is displayed. The design rules may be directly linked to the design features of the pattern library and imported into the device layout. The design rules may be directly accessed while designing the layout or while conducting a design rule check and the design features from the pattern library may be used in creating the layout.Type: GrantFiled: May 28, 2014Date of Patent: June 2, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-An Chen, Pei-Tzu Wu, Tsung-Chieh Tsai, Juing-Yi Wu, Jyh-Kang Ting
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Publication number: 20150072480Abstract: Among other things, one or more systems and techniques for defining one or more implant regions or for doping a semiconductor arrangement are provided. A first implant region is defined based upon a first implant mask overlaying a first active region of a semiconductor arrangement. A second implant region is defined based upon the first implant mask and a second implant mask overlaying a second active region of the semiconductor arrangement. A third implant region is defined based upon the second implant mask overlaying a third active region of the semiconductor arrangement. One or more doping processes are performed through the first implant mask and the second implant mask to dope the semiconductor arrangement. Because the first implant mask and the second implant mask overlap the second active region, doping area coverage is improved thus mitigating undesirable voltage threshold variations otherwise resulting from inadequate doping area coverage.Type: ApplicationFiled: September 11, 2013Publication date: March 12, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Juing-Yi Wu, Jyh-Kang Ting, Tsung-Chieh Tsai, Liang-Yao Lee
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Publication number: 20150050810Abstract: A method for ameliorating corner rounding effects in a photolithographic process is provided. A semiconductor workpiece having an active device region is provided, and a photoresist layer is formed over the semiconductor workpiece. A mask is provided for patterning for the photoresist layer, wherein the mask comprises pattern having a sharp corner associated with the active device region. The sharp corner is separated from the active device region by a first distance in a first direction and a second distance in a second direction, wherein the first distance meets a minimum criteria for the photolithographic process, and wherein the second distance is greater than the first distance. The photoresist layer is then exposed to a radiation source, and the radiation source patterns the photoresist layer through the mask, defining an exposure region on the semiconductor workpiece having a rounded corner associated with the sharp corner.Type: ApplicationFiled: August 15, 2013Publication date: February 19, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Liang-Yao Lee, Jyh-Kang Ting, Tsung-Chieh Tsai, Juing-Yu Wu
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Publication number: 20150048457Abstract: A method for mask optimization, the method including moving any features of a gate contact mask that are in violation of a spacing rule to a second layer contact mask, splitting an elongated feature of the second layer mask that is too close to a feature moved to the second layer mask from the gate contact mask, and connecting two split features of a first layer contact mask, the split features corresponding to the elongated feature of the second layer mask.Type: ApplicationFiled: August 16, 2013Publication date: February 19, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting, Chun-Yi Lee
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Publication number: 20150001734Abstract: A method includes placing two conductive lines in a layout. Two cut lines are placed over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
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Publication number: 20140282294Abstract: Provided is a system and method for designing the layout of integrated circuits or other semiconductor devices while directly accessing design rules and a library of design features by interfacing with a GUI upon which the design layout is displayed. The design rules may be directly linked to the design features of the pattern library and imported into the device layout. The design rules may be directly accessed while designing the layout or while conducting a design rule check and the design features from the pattern library may be used in creating the layout.Type: ApplicationFiled: May 28, 2014Publication date: September 18, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-An CHEN, Pei-Tzu WU, Tsung-Chieh TSAI, Juing-Yi WU, Jyh-Kang TING
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Patent number: 8806417Abstract: A target integrated circuit layout having a plurality of design rules having minimum rules and standard rules used in the target integrated circuit layout is provided. First and second design rule checks are performed, where respective first and second sets of violations of the plurality of design rules and each design rule associated with the first and second sets of violations are recorded. An analysis is performed on the first and second sets of violations, each design rule associated with the first and second sets of violations, and a frequency of usage of each of the plurality of design rules, and a rule usage rate is determined having a number of minimum rules used overall and a number of overall violations of the design rules. An interactive rule database is formed having statistics associated with the rule usage rate for subsequent implementation in an integrated circuit.Type: GrantFiled: April 26, 2013Date of Patent: August 12, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Ming Chao, Jyh-Kang Ting, Chin-An Chen, Pei-tzu Wu, Chun-Yi Lee
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Patent number: 8769475Abstract: Provided is a system and method for designing the layout of integrated circuits or other semiconductor devices while directly accessing design rules and a library of design features by interfacing with a GUI upon which the design layout is displayed. The design rules may be directly linked to the design features of the pattern library and imported into the device layout. The design rules may be directly accessed while designing the layout or while conducting a design rule check and the design features from the pattern library may be used in creating the layout.Type: GrantFiled: October 31, 2011Date of Patent: July 1, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-An Chen, Pei-Tzu Wu, Tsung-Chieh Tsai, Juing-Yi Wu, Jyh-Kang Ting
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Publication number: 20130111418Abstract: Provided is a system and method for designing the layout of integrated circuits or other semiconductor devices while directly accessing design rules and a library of design features by interfacing with a GUI upon which the design layout is displayed. The design rules may be directly linked to the design features of the pattern library and imported into the device layout. The design rules may be directly accessed while designing the layout or while conducting a design rule check and the design features from the pattern library may be used in creating the layout.Type: ApplicationFiled: October 31, 2011Publication date: May 2, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-An Chen, Pei-Tzu Mu, Tsung-Chieh Tsai, Juing-Yi Wu, Jyh-Kang Ting
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Publication number: 20130075796Abstract: A method of fabricating a semiconductor device is disclosed. A dummy gate feature is formed between two active gate features over a substrate. An isolation structure is in the substrate and the dummy gate feature is over the isolation structure. In at least one embodiment, a non-conductive material is used for forming the dummy gate feature to replace a sacrificial gate electrode.Type: ApplicationFiled: September 28, 2011Publication date: March 28, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Chieh TSAI, Yung-Che Albert SHIH, Jyh-Kang TING
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Publication number: 20070158835Abstract: A method is disclosed for determining a size of an interconnect between a first and a second conductor respectively in two layers of an integrated circuit while scaling from a reference processing technology to a predetermined processing technology. The method comprises selecting a set of design rules for the conductors based on the predetermined processing technology, determining a length of a first side of a rectangular cross sectional area of the interconnect based on the design rules and a scaling rule for scaling such a length from the reference processing technology to the predetermined processing technology, and determining a length of a second side of the cross sectional area of the interconnect for compensating an increase of a resistance of the interconnect due to the scaling from the reference processing technology to the predetermined processing technology.Type: ApplicationFiled: January 12, 2006Publication date: July 12, 2007Inventors: Jian-Hong Lin, Hsueh-Chung Chen, Yi-Lung Cheng, Ta-Wei Lee, Chih-Tao Lin, Jyh-Kang Ting, Lee-Chung Lu
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Patent number: 6169314Abstract: This invention provides a circuit layout pattern and layout method for matching pairs of metal oxide semiconductor field effect transistors used in matched pairs in precision analog circuits. The layout uses dummy Metal oxide field effect transistors, or MOSFETs, to keep the environment the same around each of the MOSFETs in a matched pair. The MOSFETs in a matched pair are in a single row with each MOSFET in the matched pair having dummy MOSFETs adjacent to it on either side. The dummy MOSFETs can be part of the matched pair, can be used in other parts of the circuit, or may not be used. The use of dummy MOSFETs keeps the environment around each MOSFET in the matched pair the same and this improves the matching characteristics.Type: GrantFiled: July 1, 1999Date of Patent: January 2, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Shyh-Chyi Wong, Pin-Nan Tseng, Jyh-Kang Ting