Abstract: A clocking scheme is provided to synchronize system clock across plural independent SMP (Symmetric Multi-Processing) domains of the multi-processor system. Each of the SMP domains is connected with another through an interconnection board and two or more identical connectors. The clocking scheme includes a clock source, a SPLL (Select Phase-Locked Loop) and a clock buffer on each of the SMP domains to provide a dedicated base clock. A self-clock path is used to send the base clock from the clock source to the SPLL on the same SMP domain, and on the other hand one or more base clock is sent through a distribution-clock path to another SPLL. The distribution-clock path and the self-clock path will have equal lengths, making the base clock pass through the two connectors or the same connector twice to achieve the similar electrical characteristics and balance the skew or propagation delay.

Abstract: A physical hardware architecture is provided to fulfill flexibility, serviceability and configurability of a multi-processor system. The architecture mainly includes a bottom plane, plural processor boards and a function board. On the front section of the top side of the bottom plane, the processor boards are configured thereon. The function board faces downwards and is configured in an edge-to-edge connection with the front edge of the bottom plane. Function card(s) may be configured vertically on the bottom surface of the function board. On the rear section of the top side of the bottom plane expansion card(s) are configured vertically. With main system fan(s) located on the top of the function board and auxiliary system fan configured under the bottom plane, the multi-processor system will also achieve optimum cooling capability through the architecture.

Abstract: A remote monitor module for power initialization of a computer system includes a monitor logic and a BMC (Baseboard Management Controller). The monitor logic is in circuit connection with a power-up sequence controller and several basic voltage domains on a system board of the computer system. The monitor logic also defines a monitor power-up sequence to perform a basic power-up sequence defined in the power-up sequence controller and allow system changes in power initialization. Extra voltage domain(s) may be enabled and monitored according to the monitor power-up sequence. Eventually, multiple power initialization event/state signals are transmitted by the monitor logic to a remote management host through the BMC.

Abstract: A scalable computer system includes a reconfigurable chassis module, plural hardware units and one or more inter-plane. The chassis module has plural modular units for configuring the hardware units therein respectively. Each of the modular units has dedicated framework to attach the inter-plane or dedicated fans. The inter-plane is to connect with the separated hardware units between the modular units. Each of the modular units is equipped with compatible male and female joints to engage with each other. Certain fastening assemblies may be applied to secure male-male or female-female joints, thereby enabling the modular units to be front-to-back and/or side-by-side connections.

Abstract: A symmetric multiprocessor computer is provided with a star interconnection architecture and a cooling system. The star interconnection architecture include a middle plane, and plural first processor boards and second processor boards configured vertically onto opposite surfaces of the middle plane. The first processor boards and the second processor boards are crisscross to each other at the opposite surfaces of the middle plane. The cooling system includes a first cooling module and a second cooling system module configured for generating a plurality of first airflows and second airflows for the first processor boards and the second processor boards respectively, wherein the paths of the first airflows and the second airflows are crisscross to each other at the opposite surfaces of the middle plane.

Abstract: A symmetric multiprocessor computer is provided with a star interconnection architecture and a cooling system. The star interconnection architecture include a middle plane, and plural first processor boards and second processor boards configured vertically onto opposite surfaces of the middle plane. The first processor boards and the second processor boards are crisscross to each other at the opposite surfaces of the middle plane. The cooling system includes a first cooling module and a second cooling system module configured for generating a plurality of first airflows and second airflows for the first processor boards and the second processor boards respectively, wherein the paths of the first airflows and the second airflows are crisscross to each other at the opposite surfaces of the middle plane.

Abstract: A three dimensional interconnection architecture is provided for a multiprocessor computer. The interconnection architecture includes multiple processor boards, one or more interconnection board and one or more edge board. The processor boards are configured parallel to each other, each having plural processors configured thereon. The interconnection board is connected with one side of each of the processor boards to allow one of the processors on one of the processor boards operatively connecting with another one of the processors on another one of the processor boards. The edge board is connected with another side of each of the processor boards to allow one of the processors on one of the processor boards operatively connecting with another one of the processors on another one of the processor boards.

Abstract: An interconnection architecture is provided for flexibly connecting a primary host module or an added host module to a network switch in a clustering system. The interconnection architecture mainly includes plural first slots, a primary function module, an added function module and plural multifunctional buses. The first slots electrically connect the network switch with the primary and added host modules. The primary function module inserts in one of the first slots to electrically connect the primary host module with the network switch; and the added function module inserts in one of the first slots to electrically connect the added host module with the network switch. The multifunctional buses connect the network switch with the first slots and also connect the first slots with the primary host module and the added host module.

Abstract: A physical hardware architecture is provided to fulfill flexibility, serviceability and configurability of a multi-processor system. The architecture mainly includes a bottom plane, plural processor boards and a function board. On the front section of the top side of the bottom plane, the processor boards are configured thereon. The function board faces downwards and is configured in an edge-to-edge connection with the front edge of the bottom plane. Function card(s) may be configured vertically on the bottom surface of the function board. On the rear section of the top side of the bottom plane expansion card(s) are configured vertically. With main system fan(s) located on the top of the function board and auxiliary system fan configured under the bottom plane, the multi-processor system will also achieve optimum cooling capability through the architecture.

Abstract: A clocking scheme is provided to synchronize system clock across plural independent SMP (Symmetric Multi-Processing) domains of the multi-processor system. Each of the SMP domains is connected with another through an interconnection board and two or more identical connectors. The clocking scheme includes a clock source, a SPLL (Select Phase-Locked Loop) and a clock buffer on each of the SMP domains to provide a dedicated base clock. A self-clock path is used to send the base clock from the clock source to the SPLL on the same SMP domain, and on the other hand one or more base clock is sent through a distribution-clock path to another SPLL.

Abstract: A chassis partition architecture of a chassis for configuring a multi-processor system is provided to fulfill flexibility, serviceability and configurability of a multi-processor system. The partition architecture mainly includes the partition architecture mainly includes a node partition, a expansion partition and a function partition. The node partition is located at a middle section of the chassis, mainly for containing several processor boards that are configured vertically and lengthwise. The expansion partition is located behind the node partition, mainly for containing several expansion boards that are configured vertically and lengthwise. And the function partition is located at a front section of the chassis lower than the node partition and the expansion partition, mainly for containing a plurality of function cards that are configured upside-down vertically and lengthwise.

Abstract: A redundant clock distribution architecture is provided for a blade clustering system to achieve SMP (symmetric multi-processor) capability and flexible system configuration. The architecture mainly provides a central clock signal from a central clock and a local clock signal from an operative local clock configured on each blade module of the system. A clock multiplexer selects the central clock signal and sends to plural local clock consumers on each blade module. The clock multiplexer switches to send the local clock signal if the central clock fails.

Abstract: A remote monitor module is provided to monitor initialization events of a computer host domain on a local mainboard. The remote module includes an event monitor to detect certain initialization events during system initialization process, and then generates and transmits event signals to a BMC (Baseboard Management Controller). A decoder may be used to decode BIOS check data at a specific I/O address and provides check data signals to the BMC. The BMC receives the event signals and/or the check data signals and transmits to a remote management host through remote management link(s).

Abstract: A system and method are provided to enable flexible symmetric multi-processor (SMP) configuration. The system includes plural bootable domains and a glue logic. The bootable domains include plural processors, one or more boot image and one or more bridge interface. Each of the bootable domains links to another through the connection between the processors. The glue logic receives and processes a configuration signal and generates enable/disable signals to enable/disable each of the bootable domains and define one or more actual boot domain. The processor of the enabled bootable domain initializes the dedicated actual boot domain by accessing boot instructions from the boot image through the bridge interface.

Abstract: A scalable computer system includes a reconfigurable chassis module, plural hardware units and one or more inter-plane. The chassis module has plural modular units for configuring the hardware units therein respectively. Each of the modular units has dedicated framework to attach the inter-plane or dedicated fans. The inter-plane is to connect with the separated hardware units between the modular units. Each of the modular units is equipped with compatible male and female joints to engage with each other. Certain fastening assemblies may be applied to secure male-male or female-female joints, thereby enabling the modular units to be front-to-back and/or side-by-side connections.

Abstract: A remote monitor module for power initialization of a computer system includes a monitor logic and a BMC (Baseboard Management Controller). The monitor logic is in circuit connection with a power-up sequence controller and several basic voltage domains on a system board of the computer system. The monitor logic also defines a monitor power-up sequence to perform a basic power-up sequence defined in the power-up sequence controller and allow system changes in power initialization. Extra voltage domain(s) may be enabled and monitored according to the monitor power-up sequence. Eventually, multiple power initialization event/state signals are transmitted by the monitor logic to a remote management host through the BMC.

Abstract: A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.

Abstract: A device configured to recover and repeat source synchronous data. The device is configured to receive source synchronous data via a first interface and recover the received data utilizing a first clock signal which is generated to be approximately ninety degrees out of phase with the received clock signal. A second clock signal is generated to be in phase with the received source synchronous clock signal. The second clock signal is the utilized to select a newly generated clock signal and latched data for transmission in a source synchronous manner. The device is further configured to shift the phase of the generated first clock signal to be approximately ninety degrees out of phase with the received data signal.

Abstract: A device configured to recover and repeat source synchronous data. In one embodiment, the device is configured to receive source synchronous data via a first interface, recover the received data utilizing a corresponding received source synchronous clock signal, and transmit the recovered data and a corresponding clock signal in a source synchronous manner. In one embodiment, the device is configured to operate as a repeater without benefit of an internal clock signal. In addition, the device may be configured to remove data jitter and renew or restore amplitude to attenuated signals prior to retransmission.

Abstract: A noise margin self-diagnostic receiver circuit has been developed. The self-diagnostic circuit includes one comparator for comparing the signal voltage to a high reference voltage, a second comparator for comparing the signal voltage to a low reference voltage, and a logic circuit that activates an alarm if a noise error is detected. The circuit analyzes the data from the comparators and determines if a noise error has occurred dependent on being clocked by one or both of an output from the comparator comparing the signal voltage to the high reference voltage and an output from the comparator comparing the signal voltage to the low reference voltage.