Patents by Inventor Jyun-Ying LIN
Jyun-Ying LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240147689Abstract: Integrated circuits (ICs) and methods are provided. An IC includes a charge-storing device. The charge-storing device includes a first charge-storing stack extending into a substrate, and a second charge-storing stack extending into the substrate and adjacent to the first charge-storing stack along a first direction. The first charge-storing stack and the second charge-storing stack extend lengthwise along a second direction perpendicular to the first direction, and the first charge-storing stack and the second charge-storing stack have an offset along the second direction, the offset being greater than zero.Type: ApplicationFiled: February 23, 2023Publication date: May 2, 2024Inventors: Ming-Hsun Lin, Jyun-Ying Lin
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Publication number: 20240014254Abstract: Various embodiments of the present application are directed towards an integrated chip (IC). The IC comprises a trench capacitor overlying a substrate. The trench capacitor comprises a plurality of capacitor electrode structures, a plurality of warping reduction structures, and a plurality of capacitor dielectric structures. The plurality of capacitor electrode structures, the plurality of warping reduction structures, and the plurality of capacitor dielectric structures are alternatingly stacked and define a trench segment that extends vertically into the substrate. The plurality of capacitor electrode structures comprise a metal component and a nitrogen component. The plurality of warping reduction structures comprise the metal component, the nitrogen component, and an oxygen component.Type: ApplicationFiled: July 11, 2022Publication date: January 11, 2024Inventors: Ting-Chen Hsu, Hsin-Li Cheng, Jyun-Ying Lin, Yingkit Felix Tsui, Shu-Hui Su, Shi-Min Wu
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Publication number: 20230378251Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a capacitor over a substrate. The capacitor includes a plurality of conductive layers and a plurality of dielectric layers. The plurality of conductive layers and dielectric layers define a base structure and a first protrusion structure extending downward from the base structure towards a bottom surface of the substrate. The first protrusion structure comprises one or more surfaces defining a first cavity. A top of the first cavity is disposed below the base structure.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Alexander Kalnitsky, Shih-Fen Huang, Shu-Hui Su, Ting-Chen Hsu, Tuo-Hsin Chien, Felix Ying-Kit Tsui, Shi-Min Wu, Yu-Chi Chang
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Publication number: 20230361166Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.Type: ApplicationFiled: June 26, 2023Publication date: November 9, 2023Inventors: Jyun-Ying Lin, Hsin-Li Cheng, Jing-Hwang Yang, Felix Ying-Kit Tsui, Chien-Li Kuo
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Patent number: 11769792Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a substrate comprising sidewalls that define a trench. A capacitor comprising a plurality of conductive layers and a plurality of dielectric layers that define a trench segment is disposed within the trench. A width of the trench segment continuously increases from a front-side surface of the substrate in a direction towards a bottom surface of the trench.Type: GrantFiled: July 8, 2021Date of Patent: September 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Alexander Kalnitsky, Shih-Fen Huang, Shu-Hui Su, Ting-Chen Hsu, Tuo-Hsin Chien, Felix Ying-Kit Tsui, Shi-Min Wu, Yu-Chi Chang
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Patent number: 11688762Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.Type: GrantFiled: November 25, 2020Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyun-Ying Lin, Hsin-Li Cheng, Jing-Hwang Yang, Felix Ying-Kit Tsui, Chien-Li Kuo
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Publication number: 20210343881Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a substrate comprising sidewalls that define a trench. A capacitor comprising a plurality of conductive layers and a plurality of dielectric layers that define a trench segment is disposed within the trench. A width of the trench segment continuously increases from a front-side surface of the substrate in a direction towards a bottom surface of the trench.Type: ApplicationFiled: July 8, 2021Publication date: November 4, 2021Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Alexander Kalnitsky, Shih-Fen Huang, Shu-Hui Su, Ting-Chen Hsu, Tuo-Hsin Chien, Felix Ying-Kit Tsui, Shi-Min Wu, Yu-Chi Chang
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Patent number: 11063157Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.Type: GrantFiled: December 27, 2019Date of Patent: July 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Alexander Kalnitsky, Shih-Fen Huang, Shu-Hui Su, Ting-Chen Hsu, Tuo-Hsin Chien, Felix Ying-Kit Tsui, Shi-Min Wu, Yu-Chi Chang
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Publication number: 20210202761Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.Type: ApplicationFiled: December 27, 2019Publication date: July 1, 2021Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Alexander Kalnitsky, Shih-Fen Huang, Shu-Hui Su, Ting-Chen Hsu, Tuo-Hsin Chien, Felix Ying-Kit Tsui, Shi-Min Wu, Yu-Chi Chang
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Publication number: 20210104598Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.Type: ApplicationFiled: November 25, 2020Publication date: April 8, 2021Inventors: Jyun-Ying Lin, Hsin-Li Cheng, Jing-Hwang Yang, Felix Ying-Kit Tsui, Chien-Li Kuo
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Patent number: 10868110Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.Type: GrantFiled: April 18, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyun-Ying Lin, Hsin-Li Cheng, Jing-Hwang Yang, Felix Ying-Kit Tsui, Chien-Li Kuo
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Patent number: 10693019Abstract: Various embodiments of the present application are directed towards a trench capacitor with a high capacitance density. In some embodiments, the trench capacitor overlies the substrate and fills a trench defined by the substrate. The trench capacitor comprises a lower capacitor electrode, a capacitor dielectric layer, and an upper capacitor electrode. The capacitor dielectric layer overlies the lower capacitor electrode and lines the trench. The upper capacitor electrode overlies the capacitor dielectric layer and lines the trench over the capacitor dielectric layer. The capacitor dielectric layer comprises a high ? dielectric material. By using a high ? material for the dielectric layer, the trench capacitor may have a high capacitance density suitable for use with high performance mobile devices.Type: GrantFiled: August 27, 2018Date of Patent: June 23, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Jing-Hwang Yang, Ting-Chen Hsu, Felix Ying-Kit Tsui, Yen-Wen Chen
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Publication number: 20200066922Abstract: Various embodiments of the present application are directed towards a trench capacitor with a high capacitance density. In some embodiments, the trench capacitor overlies the substrate and fills a trench defined by the substrate. The trench capacitor comprises a lower capacitor electrode, a capacitor dielectric layer, and an upper capacitor electrode. The capacitor dielectric layer overlies the lower capacitor electrode and lines the trench. The upper capacitor electrode overlies the capacitor dielectric layer and lines the trench over the capacitor dielectric layer. The capacitor dielectric layer comprises a high ? dielectric material. By using a high ? material for the dielectric layer, the trench capacitor may have a high capacitance density suitable for use with high performance mobile devices.Type: ApplicationFiled: August 27, 2018Publication date: February 27, 2020Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Jing-Hwang Yang, Ting-Chen Hsu, Felix Ying-Kit Tsui, Yen-Wen Chen
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Publication number: 20190245031Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.Type: ApplicationFiled: April 18, 2019Publication date: August 8, 2019Inventors: Jyun-Ying Lin, Hsin-Li Cheng, Jing-Hwang Yang, Felix Ying-Kit Tsui, Chien-Li Kuo
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Patent number: 10276651Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.Type: GrantFiled: September 1, 2017Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyun-Ying Lin, Hsin-Li Cheng, Jing-Hwang Yang, Felix Ying-Kit Tsui, Chien-Li Kuo
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Publication number: 20190074349Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.Type: ApplicationFiled: September 1, 2017Publication date: March 7, 2019Inventors: Jyun-Ying Lin, Hsin-Li Cheng, Jing-Hwang Yang, Felix Ying-Kit Tsui, Chien-Li Kuo
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Patent number: 9978829Abstract: Some embodiments relate to high density capacitor structures. Some embodiments include a first trench capacitor, a second trench capacitor and an interconnect structure. The first trench capacitor includes a first capacitor plate disposed in a plurality of trenches in a semiconductor substrate, and a second capacitor plate disposed in the plurality of trenches and separated from the first capacitor plate by a first capacitor dielectric along bottom and sidewall surfaces of the plurality of trenches. The second trench capacitor is disposed over the first trench capacitor. The second trench capacitor includes the second capacitor plate, and a third capacitor plate disposed in the plurality of trenches and separated from the second capacitor plate by a second capacitor dielectric. The interconnect structure connects the first capacitor plate and the third capacitor plate such that the first and second trench capacitors are in parallel.Type: GrantFiled: September 28, 2015Date of Patent: May 22, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Jyun-Ying Lin
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Publication number: 20160020267Abstract: Some embodiments relate to high density capacitor structures. Some embodiments include a first trench capacitor, a second trench capacitor and an interconnect structure. The first trench capacitor includes a first capacitor plate disposed in a plurality of trenches in a semiconductor substrate, and a second capacitor plate disposed in the plurality of trenches and separated from the first capacitor plate by a first capacitor dielectric along bottom and sidewall surfaces of the plurality of trenches. The second trench capacitor is disposed over the first trench capacitor. The second trench capacitor includes the second capacitor plate, and a third capacitor plate disposed in the plurality of trenches and separated from the second capacitor plate by a second capacitor dielectric. The interconnect structure connects the first capacitor plate and the third capacitor plate such that the first and second trench capacitors are in parallel.Type: ApplicationFiled: September 28, 2015Publication date: January 21, 2016Inventor: Jyun-Ying Lin
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Patent number: 9178080Abstract: Some embodiments relate to high density capacitor structures. Some embodiments include a semiconductor substrate having an conductive region with a plurality of trenches formed therein. A first dielectric layer is formed over respective bottom portions and respective sidewall portions of the respective trenches. A first conductive layer is formed in the trench and over the first dielectric layer, wherein the first dielectric layer acts as a first capacitor dielectric between the conductive region and the first conductive layer. A second dielectric layer is formed in the trench and over the first conductive layer. A second conductive layer is formed in the trench and over the second dielectric layer, wherein the second dielectric layer acts as a second capacitor dielectric between the first conductive layer and the second conductive layer. Other embodiments are also disclosed.Type: GrantFiled: November 26, 2012Date of Patent: November 3, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Alex Kalnitsky, Felix Ying-Kit Tsui, Hsin-Li Cheng, Jing-Hwang Yang, Jyun-Ying Lin
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Patent number: 8962439Abstract: A method of programming a memory cell includes causing a current to flow through a first silicide-containing portion and a second silicide-containing portion of the memory cell; and causing, by the current, an electron-migration effect to form an extended silicide-containing portion within the gap such that the memory cell is converted from a first state into a second state. The memory cell includes a silicon-containing line continuously extending between a first region and a second region; the first silicide-containing portion over the silicon-containing line and adjacent to the first region; and the second silicide-containing portion over the silicon-containing line and adjacent to the second region. The first silicide-containing portion and the second silicide-containing portion are separated by a gap if the memory cell is at the first state. The extended silicide-containing portion extends from the second silicide-containing portion towards the first silicide-containing portion.Type: GrantFiled: June 11, 2014Date of Patent: February 24, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jyun-Ying Lin, Chun-Yao Ko, Ting-Chen Hsu