Patents by Inventor K. Kumar

K. Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10078363
    Abstract: An apparatus is provided that includes a microcontroller to facilitate data communication within a system comprising a plurality of peripheral devices, a power manager to put the microcontroller into a sleep state to save power, and an I/O controller to enable communication between two or more particular peripheral devices in the plurality of peripheral devices without involvement of the microcontroller while the microcontroller is in the sleep state. The microcontroller is to wake from the sleep state in response to at least one signal from a component of the system external to the microcontroller and communication between at least some of the plurality of peripheral devices is facilitated using the microcontroller when in an awake state.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: September 18, 2018
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner D. Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty
  • Publication number: 20180176924
    Abstract: A method of wireless communication includes determining a set of subframes with a reduced likelihood of being received as uplink transmissions of a first user equipment (UE). The method also includes scheduling uplink transmissions of the first UE by scheduling uplink control information (UCI) on subframes other than the determined set of subframes.
    Type: Application
    Filed: February 15, 2018
    Publication date: June 21, 2018
    Inventors: Raj K. KUMAR, Kapil BHATTAD, Dhananjay A. GORE
  • Publication number: 20180089465
    Abstract: Systems and methods are described for rate-limiting a message-sending client interacting with a message service based on dynamically calculated risk assessments of the probability that the client is, or is not, a sender of a spam messages. The message service sends a proof of work problem to a sending client device with a difficulty level that is related to a risk assessment that the client is a sender of spam messages. The message system limits the rate at which a known or suspected spammer can send messages by giving the known or suspected spammer client harder proof of work problems to solve, while minimizing the burden on normal users of the message system by given them easier proof of work problems to solve that can typically be solved by the client within the time that it takes to type a message.
    Type: Application
    Filed: September 18, 2017
    Publication date: March 29, 2018
    Inventors: Lucas O. Winstrom, Eric D. Friedman, Ritwik K. Kumar, Jeremy M. Stober, Amol V. Pattekar, Benoit Chevallier-Mames, Julien Lerouge, Gianpaolo Fasoli, Augustin J. Farrugia, Mathieu Ciet
  • Publication number: 20180091466
    Abstract: Systems and methods are disclosed for determining whether a message received by a client may be spam, in a computing environment that preserves privacy. The message may be encrypted. A client invokes the methods when a message is received from a sender that is not known to the client. A client can decrypt the message, break the message into chunks, and apply a differentially private algorithm to the set of chunks. The client transmits the differentially private message sketches to an aggregation server. The aggregation server receives a large collection of such message sketches for a large plurality of clients. The aggregation server returns aggregated message chunk (e.g. frequency) information to the client to assist the client in determining whether the message may be spam. The client can process the message based on the determination without disclosing the message content to the server.
    Type: Application
    Filed: September 20, 2017
    Publication date: March 29, 2018
    Inventors: Eric D. Friedman, Ritwik K. Kumar, Lucas Winstrom
  • Patent number: 9930678
    Abstract: A method of wireless communication includes determining a set of subframes with a reduced likelihood of being received as uplink transmissions of a first user equipment (UE). The method also includes scheduling uplink transmissions of the first UE by scheduling uplink control information (UCI) on subframes other than the determined set of subframes.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: March 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Raj K. Kumar, Kapil Bhattad, Dhananjay A. Gore
  • Patent number: 9880932
    Abstract: A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory management unit includes logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction and to flush the dirty data from the volatile cache upon a subsequent FoF operation.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: January 30, 2018
    Assignee: Intel Corporation
    Inventors: Sanjay K. Kumar, Rajesh M. Sankaran, Subramanya R. Dulloor, Andrew V. Anderson
  • Patent number: 9846475
    Abstract: Systems and methods of enabling modulation of a frequency of a first core in a multi-core environment include logic to determine a power limit assigned to the first core, logic to determine a stall count of the first core, and logic to modulate the frequency of the first core based at least on the power limit assigned to the first core and the stall count of the first core. The first core is included in a first tile of a socket in the multi-core computer environment.
    Type: Grant
    Filed: March 31, 2012
    Date of Patent: December 19, 2017
    Assignee: Intel Corporation
    Inventor: Anil K. Kumar
  • Publication number: 20170357584
    Abstract: A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory management unit includes logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction and to flush the dirty data from the volatile cache upon a subsequent FoF operation.
    Type: Application
    Filed: August 28, 2017
    Publication date: December 14, 2017
    Applicant: Intel Corporation
    Inventors: Sanjay K. KUMAR, Rajesh M. Sankaran, Subramanya R. Dulloor, Andrew V. Anderson
  • Publication number: 20170336847
    Abstract: In one embodiment, a processor comprises: a first domain including a plurality of cores; a second domain including at least one graphics engine; and a power controller including a first logic to receive a first performance request from a driver of the second domain and to determine a maximum operating frequency for the first domain responsive to the first performance request. Other embodiments are described and claimed.
    Type: Application
    Filed: June 7, 2017
    Publication date: November 23, 2017
    Inventor: Anil K. Kumar
  • Patent number: 9803146
    Abstract: The present subject matter provides a process for hydrocarbon residue upgradation. The combination of the hydrocarbon residue along with aromatic rich hydrocarbons, catalysts and surfactants allow the operation of visbreaking unit at higher temperature while producing a stable bottom product.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: October 31, 2017
    Assignee: Hindustan Petroleum Corporation Ltd.
    Inventors: Pramod Kumar, Madan K. Kumar, Venkata Chalapathi Rao Peddy, Venkateswarlu Choudary Nettem, Sri Ganesh Gandham
  • Patent number: 9778720
    Abstract: An apparatus, system, and method, the method including receiving an indication of a idle state capability of a platform connected device; determining, by a chipset, an idle power state compatible with the device; and directing the device to enter the determined idle power state based on a power state of the chipset.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: October 3, 2017
    Assignee: Intel Corporation
    Inventors: Anil K. Kumar, John H. Crawford, Paul S. Diefenbaugh
  • Patent number: 9703358
    Abstract: In one embodiment, a processor comprises: a first domain including a plurality of cores; a second domain including at least one graphics engine; and a power controller including a first logic to receive a first performance request from a driver of the second domain and to determine a maximum operating frequency for the first domain responsive to the first performance request. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventor: Anil K. Kumar
  • Patent number: 9678793
    Abstract: Resource-based optimization is used to resolve some abnormal job terminations. An abnormal job termination is analyzed to determine if a resource shortage caused the termination. For a resource-dependent termination, the job is rescheduled for a time when sufficient resources are available.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: June 13, 2017
    Assignee: International Business Machines Corporation
    Inventors: Aruun K. Kumar, David C. Reed, Max D. Smith
  • Patent number: 9618965
    Abstract: A system for dynamically calibrating operational parameters of a Device Under Test (DUT) includes a signal generator for generating a data pattern, a DUT structured to generate a clock signal, an oscilloscope structured to measure margins of the generated clock signal compared to an eye-diagram produced on the oscilloscope from the data pattern, and a calibration unit. The calibration unit can produce a candidate a jitter value for the signal generator, receive a determination from the oscilloscope whether the data pattern generated with the candidate jitter value causes the DUT to produce the generated clock signal within a pre-determined tolerance level, and modify the jitter value accordingly. The calibration unit may also be further structured to generate voltage swing values.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: April 11, 2017
    Assignee: Tektronix, Inc.
    Inventors: Ganesh K. Kumar, Krishna N H Sri, Madhusudhan Acharya, Kamlesh Mishra
  • Publication number: 20160334833
    Abstract: A system for dynamically calibrating operational parameters of a Device Under Test (DUT) includes a signal generator for generating a data pattern, a DUT structured to generate a clock signal, an oscilloscope structured to measure margins of the generated clock signal compared to an eye-diagram produced on the oscilloscope from the data pattern, and a calibration unit. The calibration unit can produce a candidate a jitter value for the signal generator, receive a determination from the oscilloscope whether the data pattern generated with the candidate jitter value causes the DUT to produce the generated clock signal within a pre-determined tolerance level, and modify the jitter value accordingly. The calibration unit may also be further structured to generate voltage swing values.
    Type: Application
    Filed: July 30, 2015
    Publication date: November 17, 2016
    Inventors: Ganesh K. Kumar, Krishna N H Sri, Madhusudhan Acharya, Kamlesh Mishra
  • Publication number: 20160306411
    Abstract: Systems and methods of enabling power management in a micro server include providing multiple cores, a power management module coupled to the cores, and one or more peripherals coupled to the power management module. The power management module may be configured to cause the one or more peripherals to delay operations based on determining that the cores are in a first power consumption state, and place the cores in a second power consumption state for a predetermined time period. The second power consumption state may consume less power than the first power consumption state. The power management module may cause the one or more peripherals to resume their operations based on expiration of the predetermined time period and may place the cores in a third power consumption state based on the expiration of the time period.
    Type: Application
    Filed: June 27, 2016
    Publication date: October 20, 2016
    Inventor: Anil K. Kumar
  • Patent number: 9454210
    Abstract: Systems and methods of enabling power management in a micro server include providing multiple cores, a power management module coupled to the cores, and one or more peripherals coupled to the power management module. The power management module may be configured to cause the one or more peripherals to delay operations based on determining that the cores are in a first power consumption state, and place the cores in a second power consumption state for a predetermined time period. The second power consumption state may consume less power than the first power consumption state. The power management module may cause the one or more peripherals to resume their operations based on expiration of the predetermined time period and may place the cores in a third power consumption state based on the expiration of the time period.
    Type: Grant
    Filed: March 31, 2012
    Date of Patent: September 27, 2016
    Assignee: Intel Corporation
    Inventor: Anil K. Kumar
  • Publication number: 20160253208
    Abstract: Resource-based optimization is used to resolve some abnormal job terminations. An abnormal job termination is analyzed to determine if a resource shortage caused the termination. For a resource-dependent termination, the job is rescheduled for a time when sufficient resources are available.
    Type: Application
    Filed: February 26, 2015
    Publication date: September 1, 2016
    Inventors: Aruun K. Kumar, David C. Reed, Max D. Smith
  • Publication number: 20160162904
    Abstract: Techniques for managing customer satisfaction in a network workplace are presented herein. A transaction module may be configured to retrieve an indicator that describes a transaction between a consumer and a merchant. The transaction module may compare the indicator to a set of threshold indicators and may declare the transaction unsatisfactory if the response to the indicator exceeds one of the threshold indicators. A communication module may send one or more messages to the merchant in response to declaring the transaction unsatisfactory. An incentive module may determine, based on the response from the merchant, whether the merchant will provide an incentive to the consumer. In response to the merchant not providing an incentive, the incentive module may determine a system incentive to provide to the consumer.
    Type: Application
    Filed: December 5, 2014
    Publication date: June 9, 2016
    Inventors: Nithya Chellam, Harish K. Kumar, Suresh Karuppuchamy
  • Publication number: 20160147274
    Abstract: In one embodiment, a processor comprises: a first domain including a plurality of cores; a second domain including at least one graphics engine; and a power controller including a first logic to receive a first performance request from a driver of the second domain and to determine a maximum operating frequency for the first domain responsive to the first performance request. Other embodiments are described and claimed.
    Type: Application
    Filed: November 24, 2014
    Publication date: May 26, 2016
    Inventor: Anil K. Kumar