Patents by Inventor K. Reddy
K. Reddy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240119626Abstract: A system may include a controller for receiving one or more images of a metrology target including periodic features with one or more known pitches, pre-processing the one or more images using a decomposition technique to generate one or more pre-processed images, and generating one or more metrology measurements for the metrology target based on the one or more pre-processed images. Pre-processing a particular image of the one or more images may include constructing one or more trajectory matrices from the particular image, generating reconstruction components associated with the particular image from the one or more trajectory matrices using the decomposition technique, and generating a particular one of the one or more pre-processed images by based on a subset of the reconstruction components including signals with at least one of the one or more known pitches.Type: ApplicationFiled: September 22, 2023Publication date: April 11, 2024Inventors: Nireekshan K. Reddy, Vladimir Levinski
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Patent number: 11880308Abstract: A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.Type: GrantFiled: September 20, 2022Date of Patent: January 23, 2024Assignee: Apple Inc.Inventors: Ronald P. Hall, Mary D. Brown, Balaji Kadambi, Mahesh K. Reddy
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Publication number: 20230400780Abstract: A method for metrology includes directing at least one illumination beam to illuminate a semiconductor wafer on which at least first and second patterned layers have been deposited in succession, including a first target feature in the first patterned layer and a second target feature in the second patterned layer, overlaid on the first target feature. A sequence of images of the first and second target features is captured while varying one or more imaging parameters over the sequence. The images in the sequence are processed in order to identify respective centers of symmetry of the first and second target features in the images and measure variations in the centers of symmetry as a function of the varying image parameters. The measured variations are applied in measuring an overlay error between the first and second patterned layers.Type: ApplicationFiled: February 27, 2023Publication date: December 14, 2023Inventors: Amnon Manassen, Andrew V. Hill, Yonatan Vaknin, Yossi Simon, Daria Negri, Vladimir Levinski, Yuri Paskover, Anna Golotsvan, Nachshon Rothman, Nireekshan K. Reddy, Nir BenDavid, Avi Abramov, Dror Yaacov, Yoram Uziel, Nadav Gutman
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Publication number: 20230384237Abstract: A metrology system may arrange metrology measurements for a plurality of metrology targets distributed in a plurality of fields on one or samples into a signal vector, where the metrology measurements associated with the metrology targets in each of the plurality of fields are grouped within the signal vector. The system may further decompose the signal vector into reconstruction vectors associated with different spectral components of the signal vector. The system may further classify a subset of the reconstruction vectors as components of a metrology model, where a sum of the components corresponds to a metrology model describing the metrology measurements on the one or more samples. The system may further generate control signals to control one or more processing tools based on the metrology model.Type: ApplicationFiled: September 28, 2022Publication date: November 30, 2023Inventors: Nireekshan K. Reddy, Vladimir Levinski, Amnon Manassen
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Patent number: 11810174Abstract: Items within an index may be converted from classic geometry and embedded into a hyperbolic space. The hyperboloids within the hyperbolic space provide higher precision classifications of items within the index relative to their hierarchical structure. A received search query may also be converted to hyperbolic space and mapped as a query hyperboloid against an answer space that includes hyperboloids for items within the index. Distances or overlaps between the hyperboloids may be determined in order to generate a set of search results.Type: GrantFiled: March 31, 2021Date of Patent: November 7, 2023Assignee: Amazon Technologies, Inc.Inventors: Sumeet Katariya, Nikhil S. Rao, Chandan K. Reddy, Karthik Subbian, Nurendra Choudhary
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Publication number: 20230267339Abstract: In unsupervised interpretable machine learning, one or more datasets having multiple features can be received. A machine can be trained to jointly cluster and interpret resulting clusters of the dataset by at least jointly clustering the dataset into clusters and generating hyperplanes in a multi-dimensional feature space of the dataset, where the hyperplanes separate pairs of the clusters, where a hyperplane separates a pair of clusters. Jointly clustering the dataset into clusters and generating hyperplanes can repeat until convergence, where the clustering in a subsequent iteration uses the generated hyperplanes from a previous iteration to optimize performance of the clustering. The hyperplanes can be adjusted to further improve the performance of the clustering. The clusters and interpretation of the clusters can be provided, where a cluster's interpretation is provided based on hyperplanes that construct a polytope containing the cluster.Type: ApplicationFiled: February 18, 2022Publication date: August 24, 2023Inventors: Dzung Tien Phan, Connor Aram Lawless, Jayant R. Kalagnanam, Lam Minh Nguyen, Chandrasekhara K. Reddy
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Patent number: 11702957Abstract: A foundation temperature control system for use with a rotary machine is positioned between the rotary machine and a foundation. The foundation temperature control system includes a heat shield, an insulation pack positioned below the heat shield, and an air gap at least partially defined by the heat shield and the insulation pack. The heat shield, the insulation pack, and the air gap are oriented to facilitate maintaining a temperature of the foundation supporting the rotary machine below a maximum rated operating temperature of the foundation.Type: GrantFiled: November 5, 2021Date of Patent: July 18, 2023Assignee: GENERAL ELECTRIC COMPANYInventors: Rajesh K. Reddy, Jeevankumar Krishnan, Avishetti Srinivas
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Publication number: 20230151029Abstract: Disclosed herein are antimicrobial compounds, polymorphic forms, compositions, pharmaceutical compositions, the method of use and preparation thereof. Some embodiments relate to boronic acid derivatives and their use as therapeutic agents, for example, ?-lactamase inhibitors (BLIs). The boronic acid derivatives disclosed herein can be used in combination with various antibiotics to treat resistant bacteria.Type: ApplicationFiled: March 17, 2021Publication date: May 18, 2023Inventors: Raja K. Reddy, David C. Griffith, Emily Rigsbee, Serge Henri Boyer, Scott J. Hecker, Matthew Jonathan Jones
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Publication number: 20230148226Abstract: In an embodiment, the present disclosure pertains to a stable formulation of a varenicline salt or base form containing composition that prevents or reduces formation of a nitroso impurity until the end of stated expiration or longer. In some embodiments, the composition includes varenicline and at least one pharmaceutical excipient. In some embodiments, the at least one pharmaceutical excipient includes a magnesium salt and at least one of dicalcium phosphate, polyethylene glycol, or polyethylene oxide. In some embodiments, the magnesium salt can include, without limitation, magnesium aluminum silicate, magnesium aluminometasilicate, magnesium carbonate, magnesium oxide, magnesium silicate, magnesium stearate, magnesium sulfate, magnesium trisilicate, and combinations thereof. In some embodiments, a weight ratio of the varenicline to the at least one pharmaceutical excipient ranges from 1 to 99 to 99 to 1% w/w.Type: ApplicationFiled: October 28, 2022Publication date: May 11, 2023Inventors: Mansoor Khan, Ziyaur Rahman, Indra K. Reddy, Satish Dharani
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Publication number: 20230133326Abstract: In an embodiment, the present disclosure pertains to a stable formulation of a primary, secondary, and/or tertiary amino group containing composition that prevents or reduces formation of a nitroso impurity until the end of stated expiration or longer. In some embodiments, the composition includes metformin and at least one pharmaceutical excipient. In some embodiments, the at least one pharmaceutical excipient includes a magnesium salt and at least one of a calcium salt, dicalcium phosphate, polyethylene glycol, or polyethylene oxide. In some embodiments, the magnesium salt can include, without limitation, magnesium aluminum silicate, magnesium aluminometasilicate, magnesium carbonate, magnesium oxide, magnesium silicate, magnesium stearate, magnesium sulfate, magnesium trisilicate, and combinations thereof. In some embodiments, a weight ratio of the drug to the at least one pharmaceutical excipient ranges from 1 to 99 to 99 to 1% w/w.Type: ApplicationFiled: October 27, 2022Publication date: May 4, 2023Inventors: Mansoor Khan, Ziyaur Rahman, Indra K. Reddy, Satish Dharani
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Publication number: 20230128821Abstract: A computer implemented method of generating a classifier engine for machine learning includes receiving a set of data points. A semi-supervised k-means process is applied to the set of data points from each class. The set of data points in a class is clustered into multiple clusters of data points, using the semi-supervised k-means process. Multi-polytopes are constructed for one or more of the clusters from all classes. A support vector machine (SVM) process is run on every pair of clusters from all classes. Separation hyperplanes are determined for the clustered classes. Labels are determined for each cluster based on the separation by hyperplanes.Type: ApplicationFiled: September 30, 2021Publication date: April 27, 2023Inventors: Dzung Tien Phan, Lam Minh Nguyen, Jayant R. Kalagnanam, Chandrasekhara K. Reddy, Srideepika Jayaraman
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Patent number: 11630771Abstract: An apparatus includes multiple processors including respective cache memories, the cache memories configured to cache cache-entries for use by the processors. At least a processor among the processors includes cache management logic that is configured to (i) receive, from one or more of the other processors, cache-invalidation commands that request invalidation of specified cache-entries in the cache memory of the processor (ii) mark the specified cache-entries as intended for invalidation but defer actual invalidation of the specified cache-entries, and (iii) upon detecting a synchronization event associated with the cache-invalidation commands, invalidate the cache-entries that were marked as intended for invalidation.Type: GrantFiled: July 13, 2021Date of Patent: April 18, 2023Assignee: APPLE INC.Inventors: John D Pape, Mahesh K Reddy, Prasanna Utchani Varadharajan, Pruthivi Vuyyuru
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Publication number: 20230084736Abstract: A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.Type: ApplicationFiled: September 20, 2022Publication date: March 16, 2023Inventors: Ronald P. Hall, Mary D. Brown, Balaji Kadambi, Mahesh K. Reddy
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Patent number: 11599690Abstract: A computing device includes a processor and a storage device. A wafer asset modeling module is stored in the storage device and is executed by the processor to configure the computing device to perform acts identifying and clustering a plurality of assets based on static properties of a wafer asset using a first module of the wafer asset modeling module. The clustered plurality of assets is determined based on dynamic properties of the wafer asset using a second module of the wafer asset modeling module. Event prediction is performed by converting a numeric data of the clustered plurality of assets to a natural language processing (NLP) domain by a third module of the wafer asset modeling module. One or more sequence-to-sequence methods are performed to predict a malfunction of a component of the wafer asset and/or an event based on past patterns. Prediction information is stored in the storage device.Type: GrantFiled: July 20, 2020Date of Patent: March 7, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Elham Khabiri, Anuradha Bhamidipaty, Robert Jeffrey Baseman, Chandrasekhara K. Reddy, Srideepika Jayaraman
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Patent number: 11592755Abstract: A method for metrology includes directing at least one illumination beam to illuminate a semiconductor wafer on which at least first and second patterned layers have been deposited in succession, including a first target feature in the first patterned layer and a second target feature in the second patterned layer, overlaid on the first target feature. A sequence of images of the first and second target features is captured while varying one or more imaging parameters over the sequence. The images in the sequence are processed in order to identify respective centers of symmetry of the first and second target features in the images and measure variations in the centers of symmetry as a function of the varying image parameters. The measured variations are applied in measuring an overlay error between the first and second patterned layers.Type: GrantFiled: March 31, 2021Date of Patent: February 28, 2023Assignee: KLA CorporationInventors: Amnon Manassen, Andrew Hill, Yonatan Vaknin, Yossi Simon, Daria Negri, Vladimir Levinski, Yuri Paskover, Anna Golotsvan, Nachshon Rothman, Nireekshan K. Reddy, Nir BenDavid, Avi Abramov, Dror Yaacov, Yoram Uziel, Nadav Gutman
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Patent number: 11574627Abstract: Term masking is performed by generating a time-alignment value for a plurality of units of sound in vocal audio content contained in a mixed audio track, force-aligning each of the plurality of units of sound to the vocal audio content based on the time-alignment value, thereby generating a plurality of force-aligned identifiable units of sound, identifying from the plurality of force-aligned units of sound a force-aligned unit of sound to be altered, and altering the identified force-aligned unit of sound.Type: GrantFiled: July 19, 2021Date of Patent: February 7, 2023Assignee: Spotify ABInventors: Andreas Jansson, Eric J. Humphrey, Rachel Malia Bittner, Sravana K. Reddy
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Publication number: 20230017473Abstract: An apparatus includes multiple processors including respective cache memories, the cache memories configured to cache cache-entries for use by the processors. At least a processor among the processors includes cache management logic that is configured to (i) receive, from one or more of the other processors, cache-invalidation commands that request invalidation of specified cache-entries in the cache memory of the processor (ii) mark the specified cache-entries as intended for invalidation but defer actual invalidation of the specified cache-entries, and (iii) upon detecting a synchronization event associated with the cache-invalidation commands, invalidate the cache-entries that were marked as intended for invalidation.Type: ApplicationFiled: July 13, 2021Publication date: January 19, 2023Inventors: John D. Pape, Mahesh K. Reddy, Prasanna Utchani Varadharajan, Pruthivi Vuyyuru
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Patent number: 11544620Abstract: According to an embodiment of the present disclosure, a method of training a machine learning model is provided. Input data is received from at least one remote device. A classifier is evaluated by determining a classification accuracy of the input data. A training data matrix of the input data is applied to a selected context autoencoder of a knowledge bank of autoencoders including at least one context autoencoder and the training data matrix is determined to be out of context for the selected autoencoder. The training data matrix is applied to each other context autoencoder of the at least one autoencoder and the training data matrix is determined to be out of context for each other context autoencoder. A new context autoencoder is constructed.Type: GrantFiled: January 22, 2019Date of Patent: January 3, 2023Assignee: Raytheon Technologies CorporationInventors: Kin Gwn Lore, Kishore K. Reddy
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Patent number: 11524390Abstract: The present invention provides methods of manufacturing a chemical mechanical polishing (CMP polishing) layer for polishing substrates, such as semiconductor wafers comprising providing a composition of a plurality of liquid-filled microelements having a polymeric shell; classifying the composition via centrifugal air classification to remove fines and coarse particles and to produce liquid-filled microelements having a density of 800 to 1500 g/liter; and, forming the CMP polishing layer by (i) converting the classified liquid-filled microelements into gas-filled microelements by heating them, then mixing them with a liquid polymer matrix forming material and casting or molding the resulting mixture to form a polymeric pad matrix, or (ii) combining the classified liquid-filled microelements directly with the liquid polymer matrix forming material, and casting or molding.Type: GrantFiled: May 1, 2017Date of Patent: December 13, 2022Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.Inventors: Bainian Qian, George C. Jacob, Andrew Wank, David Shidner, Kancharla-Arun K. Reddy, Donna Marie Alden, Marty W. DeGroot
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Patent number: 11487667Abstract: A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.Type: GrantFiled: August 9, 2021Date of Patent: November 1, 2022Assignee: Apple Inc.Inventors: Ronald P. Hall, Mary D. Brown, Balaji Kadambi, Mahesh K. Reddy