Patents by Inventor K. Thomas
K. Thomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250151355Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.Type: ApplicationFiled: January 10, 2025Publication date: May 8, 2025Applicant: Intel CorporationInventors: Hubert C. George, Ravi Pillarisetty, Jeanette M. Roberts, Nicole K. Thomas, James S. Clarke
-
Patent number: 12292608Abstract: Gallium nitride (GaN) integrated circuit technology with optical communication is described. In an example, an integrated circuit structure includes a layer or substrate having a first region and a second region, the layer or substrate including gallium and nitrogen. A GaN-based device is in or on the first region of the layer or substrate. A CMOS-based device is over the second region of the layer or substrate. An interconnect structure is over the GaN-based device and over the CMOS-based device, the interconnect structure including conductive interconnects and vias in a dielectric layer. A photonics waveguide is over the interconnect structure, the photonics waveguide including silicon, and the photonics waveguide bonded to the dielectric layer of the interconnect structure.Type: GrantFiled: September 15, 2021Date of Patent: May 6, 2025Assignee: Intel CorporationInventors: Han Wui Then, Marko Radosavljevic, Nicole K. Thomas, Pratik Koirala, Nityan Nair, Paul B. Fischer
-
Patent number: 12266699Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.Type: GrantFiled: July 6, 2021Date of Patent: April 1, 2025Assignee: Intel CorporationInventors: Hubert C. George, Ravi Pillarisetty, Jeanette M. Roberts, Nicole K. Thomas, James S. Clarke
-
Publication number: 20250107221Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second direction perpendicular to the first direction.Type: ApplicationFiled: December 5, 2024Publication date: March 27, 2025Applicant: Intel CorporationInventors: James S. Clarke, Nicole K. Thomas, Zachary R. Yoscovits, Hubert C. George, Jeanette M. Roberts, Ravi Pillarisetty
-
Patent number: 12229889Abstract: An agricultural modeling system may include a scanning platform configured to generate 3D point cloud data of an agricultural geographic area, a geospatial database configured to store a data layer for the agricultural geographic area, and a computing resource in communication with the scanning platform, client devices, and the geospatial database. The computing resource may be configured to geographically reference the data layer fused with the 3D point cloud data of the agricultural geographic area, and generate a multi-layered data model for the geographically referenced data layer fused with the 3D point cloud data of the agricultural geographic area. A client device may be configured to selectively render the multi-layered data model.Type: GrantFiled: December 1, 2023Date of Patent: February 18, 2025Assignee: AGERPOINT, INC.Inventors: K. Thomas McPeek, Karl Steddom, Pengfei Xuan, Hemanth Kalluri, Chima Obi, Paras Pant, Angela Kim
-
Patent number: 12211841Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second direction perpendicular to the first direction.Type: GrantFiled: May 3, 2023Date of Patent: January 28, 2025Assignee: Intel CorporationInventors: James S. Clarke, Nicole K. Thomas, Zachary R. Yoscovits, Hubert C. George, Jeanette M. Roberts, Ravi Pillarisetty
-
Patent number: 12175066Abstract: At an electronic device, a user input is detected that corresponds to a respective user interface element in a portion of a user interface that is associated with a first standard gesture recognizer and a first supplemental gesture recognizer. The user input is processed in accordance with the first standard gesture recognizer and the first supplemental gesture recognizer. In accordance with a determination that content associated with the respective user interface element cannot be added to a drag operation, the device fails to recognize the user input using the first supplemental gesture recognizer, and processes the user input using the first standard gesture recognizer. On the other hand, in accordance with a determination that the content associated with the respective user interface element can be added to the drag operation, a gesture is recognized using the first supplemental gesture recognizer and the content is added to the drag operation.Type: GrantFiled: July 12, 2023Date of Patent: December 24, 2024Assignee: APPLE INC.Inventors: Bruce D. Nilo, Christopher K. Thomas, Dominik Wagner, Michael T. Turner
-
Patent number: 12148747Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.Type: GrantFiled: September 25, 2020Date of Patent: November 19, 2024Assignee: Intel CorporationInventors: Han Wui Then, Marko Radosavljevic, Pratik Koirala, Nicole K. Thomas, Paul B. Fischer, Adel A. Elsherbini, Tushar Talukdar, Johanna M. Swan, Wilfred Gomes, Robert S. Chau, Beomseok Choi
-
Patent number: 12139136Abstract: A computer, including a processor and a memory, the memory including instructions to be executed by the processor to, based on sensor data in a vehicle, determine a database that includes object data for a plurality of objects, including, for each object, an object identification, a measurement of one or more object attributes, and an uncertainty specifying a probability of correct object identification, for the object identification and the object attributes determined based on the sensor data, wherein the object attributes include an object size, an object shape and an object location. The instructions include further instructions to determine a map based on the database including the respective locations and corresponding uncertainties for the vehicle type and download the map to a vehicle based on the vehicle location and the vehicle type.Type: GrantFiled: March 25, 2020Date of Patent: November 12, 2024Assignee: Ford Global Technologies, LLCInventors: Shreyasha Paudel, Marcos Paul Gerardo Castro, Sandhya Bhaskar, Clifton K. Thomas
-
Publication number: 20240269235Abstract: Provided are serum half-life extended-IL-2 variant (IL-2v) heterodimers having reduced binding to the IL2R? (CD25) subunit. In particular, Fc-IL-2v heterodimers are provided and methods for making and using, e.g. for enhancing an immune response, e.g. in the prevention and treatment of viral infections and cancer.Type: ApplicationFiled: December 14, 2023Publication date: August 15, 2024Inventors: Manuel Baca, Sarah A. Gilmore, Magdeleine S. Hung, Hassan Javanbakht, Manu Kanwar, Shahzada Khan, Prasenjit K. Mukherjee, Mark R. Nagel, Giuseppe Papalia, Danny W. Tam, Majlinda K. Thomas
-
Patent number: 11996411Abstract: Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.Type: GrantFiled: June 26, 2020Date of Patent: May 28, 2024Assignee: Intel CorporationInventors: Cheng-Ying Huang, Gilbert Dewey, Anh Phan, Nicole K. Thomas, Urusa Alaan, Seung Hoon Sung, Christopher M. Neumann, Willy Rachmady, Patrick Morrow, Hui Jae Yoo, Richard E. Schenker, Marko Radosavljevic, Jack T. Kavalieros, Ehren Mannebach
-
Publication number: 20240135351Abstract: Implementations described herein relate to systems, methods and computer-readable media to provide high availability computer architectures for performing real-time authorization of transactions. In some implementations, the method includes receiving, at two or more groups of authorization control pods, transaction information about the transaction from a payment network, wherein each authorization control pod includes a processing service, a database service, and a policy agent; processing, at a corresponding policy agent of a single authorization control pod of the two or more groups of the authorization control pods, the transaction information by comparing one or more transaction attributes in the transaction information combined with contextual and historic data against one or more policies stored in the database service; and based on the comparison, transmitting one of an approval or a rejection of the transaction to the payment network.Type: ApplicationFiled: January 1, 2024Publication date: April 25, 2024Applicant: Zact Inc.Inventors: Ioannis Georgiadis, John K. Thomas
-
Patent number: 11942516Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.Type: GrantFiled: March 25, 2022Date of Patent: March 26, 2024Assignee: Intel CorporationInventors: Nicole K. Thomas, Ravi Pillarisetty, Kanwaljit Singh, Hubert C. George, David J. Michalak, Lester Lampert, Zachary R. Yoscovits, Roman Caudillo, Jeanette M. Roberts, James S. Clarke
-
Publication number: 20240074677Abstract: A monitoring apparatus and method includes a monitor, a sensor comprising a wireless connection with the monitor, and an adapter comprising the wireless connection with the monitor and a wired or wireless connection with a remote monitoring station. The monitor is designed to wirelessly pair with the sensor and/or the adapter when being only positioned by a user in a closed proximity to the sensor and/or the adapter or in a direct contact with the sensor and/or the adapter and without an additional action by the user and/or a wired connection between the monitor and the sensor and/or the adapter. A pairing alignment mark may be provided on each of the monitor, sensor and adapter.Type: ApplicationFiled: November 10, 2023Publication date: March 7, 2024Applicant: TIDI Products, LLCInventors: Justin K. Thomas, Samantha L. McCarthy, Eduardo Hernandez, Brian Nathan Young, Melissa Waldroup, Joe Samz
-
Patent number: 11895105Abstract: An access control system is provided to prevent the surreptitious granting of access to privacy related functionality on an electronic device. Software-based events to grant access to device functionality can be validated by confirming that the software event corresponds with a hardware input event. This validation prevents the spoofing of a user interface input that may be used to fraudulently grant access to specific functionality.Type: GrantFiled: January 29, 2021Date of Patent: February 6, 2024Assignee: Apple, Inc.Inventors: James R. Montgomerie, Jessica Aranda, Patrick Coffman, Julien Freudiger, Matthew Hansen Gamble, Ron Huang, Anant Jain, Glen S. Low, Andrey Pokrovskiy, Stephen J. Rhee, Matthew E. Shepherd, Ansh Shukla, Katherine Skinner, Kyle Martin Sluder, Christopher Soli, Christopher K. Thomas, Guy L. Tribble, John Wilander
-
Patent number: 11887089Abstract: Implementations described herein relate to dynamic and predictive updating of a payment attribute of a payment instrument. In some implementations, the method includes receiving, at a computing device, route data for a plurality of trips, receiving, at the computing device, first trip data for the first trip from the user device, wherein the first trip data includes at least location data of the user device, calculating, based on the received first trip data, a fuel likelihood score for the first trip, comparing the fuel likelihood score to a first threshold, based on a determination that the fuel likelihood score meets the first threshold: transmitting, to a computer associated with a payment network, a message to update one or more payment attributes stored at the payment network and associated with the first payment instrument, and displaying an indication that the first payment instrument is approved for the fuel transaction.Type: GrantFiled: September 28, 2021Date of Patent: January 30, 2024Assignee: Zact, Inc.Inventors: Ioannis Georgiadis, Gopalakrishnan Hariharan, John K. Thomas
-
Patent number: 11880938Abstract: An agricultural modeling system may include a mobile ranging platform configured to generate 3D point cloud data of an agricultural geographic area, client devices, a geospatial database configured to store a data layer for the agricultural geographic area, and a server computing resource in communication with the mobile ranging platform, the client devices, and the geospatial database. The server computing resource may be configured to geographically reference the data layer fused with the 3D point cloud data of the agricultural geographic area, and generate a multi-layered data model for the geographically referenced data layer fused with the 3D point cloud data of the agricultural geographic area. A client device may be configured to selectively render the multi-layered data model.Type: GrantFiled: September 21, 2022Date of Patent: January 23, 2024Assignee: AGERPOINT, INC.Inventors: K. Thomas McPeek, Karl Steddom, Pengfei Xuan, Hemanth Kalluri, Chima Obi, Paras Pant, Angela Kim
-
Publication number: 20240006499Abstract: An integrated circuit includes an upper semiconductor body extending in a first direction from an upper source region to an upper drain region, and a lower semiconductor body extending in the first direction from a lower source region to a lower drain region. The upper body is spaced vertically from the lower body in a second direction orthogonal to the first direction. A gate spacer structure is adjacent to the upper and lower source regions. In an example, the gate spacer structure includes (i) a first section having a first dimension in the first direction, and (ii) a second section having a second dimension in the first direction. In an example, the first dimension is different from the second dimension by at least 1 nm. In some cases, an intermediate portion of the gate spacer structure extends laterally within a given gate structure, or between upper and lower gate structures.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: Cheng-Ying Huang, Kai Loon Cheong, Pooja Nath, Susmita Ghose, Rambert Nahm, Natalie Briggs, Charles C. Kuo, Nicole K. Thomas, Munzarin F. Qayyum, Marko Radosavljevic, Jack T. Kavalieros, Thoe Michaelos, David Kohen
-
Publication number: 20230420562Abstract: Techniques are provided herein to form non-planar semiconductor devices in a stacked transistor configuration adjacent to stressor materials. In one example, an n-channel device and a p-channel device may both be gate-all-around transistors each having any number of nanoribbons extending in the same direction, where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and both ends of the p-channel device. On the opposite side of the stacked source or drain regions (e.g., opposite from the nanoribbons), stressor materials may be used to fill the gate trench in place of additional semiconductor devices. The stressor materials may include, for instance, a compressive stressor material adjacent to the p-channel device and/or a tensile stressor material adjacent to the n-channel device. The stressor material(s) may form or otherwise be part of a diffusion cut structure.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Cheng-Ying Huang, Munzarin F. Qayyum, Nicole K. Thomas, Rohit Galatage, Patrick Morrow, Jami A. Wiedemer, Marko Radosavljevic, Jack T. Kavalieros
-
Publication number: 20230420460Abstract: An integrated circuit structure includes a device layer including an upper device above a lower device. The upper device includes an upper source or drain region, and an upper source or drain contact coupled to the upper source or drain region. The lower device includes a lower source or drain region. A first conductive feature is below the device layer, where the first conductive feature is coupled to the lower source or drain region. A second conductive feature vertically extends through the device layer. In an example, the second conductive feature is to couple (i) the first conductive feature below the device layer and (ii) an interconnect structure above the device layer. Thus, the first and second conductive features facilitate a connection between the interconnect structure on the frontside of the integrated circuit and the lower source or drain region towards the backside of the integrated circuit.Type: ApplicationFiled: June 23, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Cheng-Ying Huang, Patrick Morrow, Quan Shi, Rohit Galatage, Nicole K. Thomas, Munzarin F. Qayyum, Jami A. Wiedemer, Gilbert Dewey, Mauro J. Kobrinsky, Marko Radosavljevic, Jack T. Kavalieros