Abstract: A method includes forming a structure having a dummy gate stack over a multi-layer stack (ML) disposed on a semiconductor substrate, the ML including alternating channel layers and non-channel layers; recessing the ML in source/drain (S/D) regions; removing the non-channel layers to form first openings between the channel layers; depositing a dielectric material in the first openings; recessing the dielectric material to form undercuts; forming inner spacers in the undercuts; forming epitaxial S/D features in the S/D regions; removing the dummy gate stack to form a gate trench; removing the dielectric material from the gate trench to form second openings between the channel layers; and forming a metal gate stack in the gate trench and the second openings.

Abstract: An embodiment method includes: forming a dielectric-containing substrate over a semiconductor substrate; forming a stack of first semiconductor layers and second semiconductor layers over the dielectric-containing substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and alternate with one another within the stack; patterning the first semiconductor layer and the second semiconductor layers into a fin structure such that the fin structure includes sacrificial layers including the second semiconductor layers and channel layers including the first semiconductor layers; forming source/drain features adjacent to the sacrificial layers and the channel layers; removing the sacrificial layers of the fin structure so that the channel layers of the fin structure are exposed; and forming a gate structure around the exposed channel layers, wherein the dielectric-containing substrate is interposed between the gate structure and the semiconductor substra

Abstract: A method includes providing a substrate having an n-type fin-like field-effect transistor (NFET) region and forming a fin structure in the NFET region. The fin structure includes a first layer having a first semiconductor material, and a second layer under the first layer and having a second semiconductor material different from the first semiconductor material. The method further includes forming a patterned hard mask to fully expose the fin structure in gate regions of the NFET region and partially expose the fin structure in at least one source/drain (S/D) region of the NFET region. The method further includes oxidizing the fin structure not covered by the patterned hard mask, wherein the second layer is oxidized at a faster rate than the first layer. The method further includes forming an S/D feature over the at least one S/D region of the NFET region.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures vertically stacked and separated from one another, a source/drain feature adjacent to the plurality of nanostructures, and an inner spacer layer. The inner spacer layer includes a vertical portion interposing between the plurality of nanostructures and the source/drain feature and a plurality of horizontal portions interposing between the nanostructures. A source/drain junction is located in the vertical portion of the inner spacer layer and is spaced apart from the plurality of nanostructures by a distance.

Abstract: An embodiment method includes: forming a dielectric-containing substrate over a semiconductor substrate; forming a stack of first semiconductor layers and second semiconductor layers over the dielectric-containing substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and alternate with one another within the stack; patterning the first semiconductor layer and the second semiconductor layers into a fin structure such that the fin structure includes sacrificial layers including the second semiconductor layers and channel layers including the first semiconductor layers; forming source/drain features adjacent to the sacrificial layers and the channel layers; removing the sacrificial layers of the fin structure so that the channel layers of the fin structure are exposed; and forming a gate structure around the exposed channel layers, wherein the dielectric-containing substrate is interposed between the gate structure and the semiconductor substra

Abstract: Semiconductor devices and methods are provided. In an embodiment, a method includes providing a workpiece including a first hard mask layer on a top surface of a substrate, performing an ion implantation process to form a doped region in the substrate, after the performing of the ion implantation process, annealing the workpiece at temperature T1. The method also includes selectively removing the first hard mask layer, after the selectively removing of the first hard mask layer, performing a pre-bake process at temperature T2, and, after the performing of the pre-bake process, epitaxially growing a vertical stack of alternating channel layers and sacrificial layers on the substrate, where the temperature T2 is lower than the temperature T1.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. A semiconductor device structure is provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a gate structure formed over the first nanostructures. The semiconductor structure includes a source/drain (S/D) structure formed adjacent to the gate structure, and a silicide layer formed on a sidewall surface of the S/D structure. The semiconductor structure also includes an S/D contact structure formed over the silicide layer, and the S/D contact structure extends from a first position to a second position The first position is higher than the top surface of the gate structure, and the second position is below the bottommost nanostructure.

Abstract: A method includes forming a gate stack over a fin of a substrate; sequentially depositing a first dielectric layer, a second dielectric layer, a third dielectric layer, and a filling dielectric over the gate stack, wherein the second dielectric layer has a lower dielectric constant than dielectric constants of the first and third dielectric layers; forming a dielectric cap over the first, second, third dielectric layers and the filling dielectric; etching the dielectric cap, the first, second, third dielectric layers, and the filling dielectric simultaneously, to form gate spacers on opposite sidewalls of the gate stack and expose a top surface of the fin; and after the gate spacers are formed, forming an epitaxy source/drain structure in contact with one of the gate spacers and the top surface of the fin.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures vertically stacked and separated from one another. The semiconductor structure also includes a gate stack wrapping around the plurality of nanostructures. The semiconductor structure also includes a source/drain feature adjacent to the plurality of nanostructures. The semiconductor structure also includes a semiconductor inner spacer layer interposing between the gate stack and the source/drain feature and interposing between the plurality of nanostructures and the source/drain feature.

Abstract: A method includes forming a gate stack over a fin of a substrate; sequentially depositing a first dielectric layer, a second dielectric layer, a third dielectric layer, and a filling dielectric over the gate stack, wherein the second dielectric layer has a lower dielectric constant than dielectric constants of the first and third dielectric layers; forming a dielectric cap over the first, second, third dielectric layers and the filling dielectric; etching the dielectric cap, the first, second, third dielectric layers, and the filling dielectric simultaneously, to form gate spacers on opposite sidewalls of the gate stack and expose a top surface of the fin; and after the gate spacers are formed, forming an epitaxy source/drain structure in contact with one of the gate spacers and the top surface of the fin.

Abstract: A semiconductor device includes a first channel region disposed over a substrate, a first source region and a first drain region disposed over the substrate and connected to the first channel region such that the first channel region is disposed between the first source region and the first drain region, a gate dielectric layer disposed on and wrapping the first channel region, a gate electrode layer disposed on the gate dielectric layer and wrapping the first channel region, and a second source region and a second drain region disposed over the substrate and below the first source region and the first drain region, respectively. The second source region and the second drain region are in contact with the gate dielectric layer. A lattice constant of the first source region and the first drain region is different from a lattice constant of the second source region and the second drain region.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a semiconductor substrate and a gate stack wrapped around the channel structures. The semiconductor device structure also includes a source/drain epitaxial structure adjacent to the channel structures and multiple inner spacers. Each of the inner spacers is between the gate stack and the source/drain epitaxial structure. The semiconductor device structure further includes multiple epitaxial structures separating the inner spacers from the source/drain epitaxial structure.

Abstract: A semiconductor device includes a first channel region disposed over a substrate, a first source region and a first drain region disposed over the substrate and connected to the first channel region such that the first channel region is disposed between the first source region and the first drain region, a gate dielectric layer disposed on and wrapping the first channel region, a gate electrode layer disposed on the gate dielectric layer and wrapping the first channel region, and a second source region and a second drain region disposed over the substrate and below the first source region and the first drain region, respectively. The second source region and the second drain region are in contact with the gate dielectric layer. A lattice constant of the first source region and the first drain region is different from a lattice constant of the second source region and the second drain region.

Abstract: Methods and devices of providing tensile/compressive stressor layers for gate-all-around devices. A first GAA device and a second GAA are disposed having a shallow trench isolation feature and one of more stressor layers between gate structures of the first GAA device and the second GAA. The stressor layers can provide tensile stress to a channel layer of the first GAA device and a compressive stress to another channel layer of the second GAA device.

Abstract: The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a first fin structure disposed over an n-type FinFET (NFET) region of a substrate. The first fin structure includes a silicon (Si) layer, a silicon germanium oxide (SiGeO) layer disposed over the silicon layer and a germanium (Ge) feature disposed over the SiGeO layer. The device also includes a second fin structure over the substrate in a p-type FinFET (PFET) region. The second fin structure includes the silicon (Si) layer, a recessed silicon germanium oxide (SiGeO) layer disposed over the silicon layer, an epitaxial silicon germanium (SiGe) layer disposed over the recessed SiGeO layer and the germanium (Ge) feature disposed over the epitaxial SiGe layer.

Abstract: A semiconductor device includes a first region, a second region, a third region, and a fourth region. The first region includes a first portion of an N-well and a plurality of P-type transistors formed over the first portion of the N-well. The first region extends in a first direction. The second region includes a first portion of a P-well and a plurality of N-type transistors formed over the first portion of the P-well. The second region extends in the first direction. The third region includes a second portion of the P-well. The fourth region includes a second portion of the N-well. The first region and the second region are disposed between the third region and the fourth region.

Abstract: A semiconductor device includes a first region, a second region, a third region, and a fourth region. The first region includes a first portion of an N-well and a plurality of P-type transistors formed over the first portion of the N-well. The first region extends in a first direction. The second region includes a first portion of a P-well and a plurality of N-type transistors formed over the first portion of the P-well. The second region extends in the first direction. The third region includes a second portion of the P-well. The fourth region includes a second portion of the N-well. The first region and the second region are disposed between the third region and the fourth region.

Abstract: A method includes forming a gate stack over a fin of a substrate; sequentially depositing a first dielectric layer, a second dielectric layer, a third dielectric layer, and a filling dielectric over the gate stack, wherein the second dielectric layer has a lower dielectric constant than dielectric constants of the first and third dielectric layers; forming a dielectric cap over the first, second, third dielectric layers and the filling dielectric; etching the dielectric cap, the first, second, third dielectric layers, and the filling dielectric simultaneously, to form gate spacers on opposite sidewalls of the gate stack and expose a top surface of the fin; and after the gate spacers are formed, forming an epitaxy source/drain structure in contact with one of the gate spacers and the top surface of the fin.

Abstract: A method includes providing a substrate having an n-type fin-like field-effect transistor (NFET) region and forming a fin structure in the NFET region. The fin structure includes a first layer having a first semiconductor material, and a second layer under the first layer and having a second semiconductor material different from the first semiconductor material. The method further includes forming a patterned hard mask to fully expose the fin structure in gate regions of the NFET region and partially expose the fin structure in at least one source/drain (S/D) region of the NFET region. The method further includes oxidizing the fin structure not covered by the patterned hard mask, wherein the second layer is oxidized at a faster rate than the first layer. The method further includes forming an S/D feature over the at least one S/D region of the NFET region.

Abstract: An embodiment method includes: forming a dielectric-containing substrate over a semiconductor substrate; forming a stack of first semiconductor layers and second semiconductor layers over the dielectric-containing substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and alternate with one another within the stack; patterning the first semiconductor layer and the second semiconductor layers into a fin structure such that the fin structure includes sacrificial layers including the second semiconductor layers and channel layers including the first semiconductor layers; forming source/drain features adjacent to the sacrificial layers and the channel layers; removing the sacrificial layers of the fin structure so that the channel layers of the fin structure are exposed; and forming a gate structure around the exposed channel layers, wherein the dielectric-containing substrate is interposed between the gate structure and the semiconductor substra