Abstract: A field effect transistor includes a substrate and spacers over the substrate. The field effect transistor includes a channel recess cavity between the spacers, wherein a bottom-most surface of the channel recess cavity is parallel to the substrate top surface. The field effect transistor includes a gate stack, wherein the gate stack includes a bottom portion in the channel recess cavity and a top portion outside the channel recess cavity, the gate stack further includes a gate dielectric layer extending from the channel recess cavity along sidewalls of each of the pair of spacers, and the gate dielectric layer directly contacts the substrate below substrate top surface. The field effect transistor includes a strained source/drain (S/D) below the substrate top surface, wherein the strained S/D extends below the gate stack. The field effect transistor further includes a source/drain (S/D) extension substantially conformably surrounding the strained S/D.

Abstract: A method includes providing a substrate having an n-type fin-like field-effect transistor (NFET) region and forming a fin structure in the NFET region. The fin structure includes a first layer having a first semiconductor material, and a second layer under the first layer and having a second semiconductor material different from the first semiconductor material. The method further includes forming a patterned hard mask to fully expose the fin structure in gate regions of the NFET region and partially expose the fin structure in at least one source/drain (S/D) region of the NFET region. The method further includes oxidizing the fin structure not covered by the patterned hard mask, wherein the second layer is oxidized at a faster rate than the first layer. The method further includes forming an S/D feature over the at least one S/D region of the NFET region.

Abstract: An embodiment method includes: forming a dielectric-containing substrate over a semiconductor substrate; forming a stack of first semiconductor layers and second semiconductor layers over the dielectric-containing substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and alternate with one another within the stack; patterning the first semiconductor layer and the second semiconductor layers into a fin structure such that the fin structure includes sacrificial layers including the second semiconductor layers and channel layers including the first semiconductor layers; forming source/drain features adjacent to the sacrificial layers and the channel layers; removing the sacrificial layers of the fin structure so that the channel layers of the fin structure are exposed; and forming a gate structure around the exposed channel layers, wherein the dielectric-containing substrate is interposed between the gate structure and the semiconductor substra

Abstract: Methods are disclosed herein for forming fin-like field effect transistors (FinFETs) that maximize strain in channel regions of the FinFETs. An exemplary method includes forming a fin having a first width over a substrate. The fin includes a first semiconductor material, a second semiconductor material disposed over the first semiconductor material, and a third semiconductor material disposed over the second semiconductor material. A portion of the second semiconductor material is oxidized, thereby forming a second semiconductor oxide material. The third semiconductor material is trimmed to reduce a width of the third semiconductor material from the first width to a second width. The method further includes forming an isolation feature adjacent to the fin. The method further includes forming a gate structure over a portion of the fin, such that the gate structure is disposed between source/drain regions of the fin.

Abstract: The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with source/drain (S/D) features and a high-k/metal gate (HK/MG). A first HK/MG in a first gate region wraps over an upper portion of a first fin structure, the first fin structure including an epitaxial silicon (Si) layer as its upper portion and an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion, and the substrate as its bottom portion. A second HK/MG in a second gate region, wraps over an upper portion of a second fin structure, the second fin structure including an epitaxial SiGe layer as its upper portion, an epitaxial Si layer as it upper middle portion, an epitaxial SiGe layer as its lower middle portion, and the substrate as its bottom portion.

Abstract: Various methods are disclosed herein for fabricating non-planar circuit devices having strain-producing features. An exemplary method includes forming a fin structure that includes a first portion that includes a first semiconductor material and a second portion that includes a second semiconductor material that is different than the first semiconductor material. The method further includes forming a masking layer over a source region and a drain region of the fin structure, forming a strain-producing feature over the first portion of the fin structure in a channel region, removing the masking layer and forming an isolation feature over the strain-producing feature, forming an epitaxial feature over the second portion of the fin structure in the source region and the drain region, and performing a gate replacement process to form a gate structure over the second portion of the fin structure in the channel region.

Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the first channel layers, a gate electrode layer disposed on the gate dielectric layer and wrapping each of the first channel layers, and a liner semiconductor layer disposed between the first channel layers and the first source/drain region.

Abstract: A semiconductor device includes a first channel region disposed over a substrate, a first source region and a first drain region disposed over the substrate and connected to the first channel region such that the first channel region is disposed between the first source region and the first drain region, a gate dielectric layer disposed on and wrapping the first channel region, a gate electrode layer disposed on the gate dielectric layer and wrapping the first channel region, and a second source region and a second drain region disposed over the substrate and below the first source region and the first drain region, respectively. The second source region and the second drain region are in contact with the gate dielectric layer. A lattice constant of the first source region and the first drain region is different from a lattice constant of the second source region and the second drain region.

Abstract: Methods are disclosed herein for forming fin-like field effect transistors (FinFETs) that maximize strain in channel regions of the FinFETs. An exemplary method includes forming a fin having a first width over a substrate. The fin includes a first semiconductor material, a second semiconductor material disposed over the first semiconductor material, and a third semiconductor material disposed over the second semiconductor material. A portion of the second semiconductor material is oxidized, thereby forming a second semiconductor oxide material. The third semiconductor material is trimmed to reduce a width of the third semiconductor material from the first width to a second width. The method further includes forming an isolation feature adjacent to the fin. The method further includes forming a gate structure over a portion of the fin, such that the gate structure is disposed between source/drain regions of the fin.

Abstract: A finFET semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first fin formed in a first semiconducting layer, a second fin formed in a second semiconductor layer, and an insulating layer disposed between the first fin and the second fin. The first fin, the second fin, and the insulating layer form a stacked structure above a substrate. Sidewalls of the first fin are substantially more vertical than sidewalls of the second fin.

Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the first channel layers, a gate electrode layer disposed on the gate dielectric layer and wrapping each of the first channel layers, and a liner semiconductor layer disposed between the first channel layers and the first source/drain region.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures vertically stacked and separated from one another. The semiconductor structure also includes a gate stack wrapping around the plurality of nanostructures. The semiconductor structure also includes a source/drain feature adjacent to the plurality of nanostructures. The semiconductor structure also includes a semiconductor inner spacer layer interposing between the gate stack and the source/drain feature and interposing between the plurality of nanostructures and the source/drain feature.

Abstract: A semiconductor device includes a first region, a second region, a third region, and a fourth region. The first region includes a first portion of an N-well and a plurality of P-type transistors formed over the first portion of the N-well. The first region extends in a first direction. The second region includes a first portion of a P-well and a plurality of N-type transistors formed over the first portion of the P-well. The second region extends in the first direction. The third region includes a second portion of the P-well. The fourth region includes a second portion of the N-well. The first region and the second region are disposed between the third region and the fourth region.

Abstract: An embodiment method includes: forming a dielectric-containing substrate over a semiconductor substrate; forming a stack of first semiconductor layers and second semiconductor layers over the dielectric-containing substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and alternate with one another within the stack; patterning the first semiconductor layer and the second semiconductor layers into a fin structure such that the fin structure includes sacrificial layers including the second semiconductor layers and channel layers including the first semiconductor layers; forming source/drain features adjacent to the sacrificial layers and the channel layers; removing the sacrificial layers of the fin structure so that the channel layers of the fin structure are exposed; and forming a gate structure around the exposed channel layers, wherein the dielectric-containing substrate is interposed between the gate structure and the semiconductor substra

Abstract: A semiconductor device includes a first channel region disposed over a substrate, a first source region and a first drain region disposed over the substrate and connected to the first channel region such that the first channel region is disposed between the first source region and the first drain region, a gate dielectric layer disposed on and wrapping the first channel region, a gate electrode layer disposed on the gate dielectric layer and wrapping the first channel region, and a second source region and a second drain region disposed over the substrate and below the first source region and the first drain region, respectively. The second source region and the second drain region are in contact with the gate dielectric layer. A lattice constant of the first source region and the first drain region is different from a lattice constant of the second source region and the second drain region.

Abstract: A field effect transistor includes a substrate and spacers over the substrate. The field effect transistor includes a channel recess cavity between the spacers, wherein a bottom-most surface of the channel recess cavity is parallel to the substrate top surface. The field effect transistor includes a gate stack, wherein the gate stack includes a bottom portion in the channel recess cavity and a top portion outside the channel recess cavity, the gate stack further includes a gate dielectric layer extending from the channel recess cavity along sidewalls of each of the pair of spacers, and the gate dielectric layer directly contacts the substrate below substrate top surface. The field effect transistor includes a strained source/drain (S/D) below the substrate top surface, wherein the strained S/D extends below the gate stack. The field effect transistor further includes a source/drain (S/D) extension substantially conformably surrounding the strained S/D.

Abstract: A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a side of the gate stack and connected to the semiconductor fin. The source/drain region includes an inner portion thinner than the semiconductor fin, and an outer portion outside the inner portion. The semiconductor fin and the inner portion of the source/drain region have a same composition of group IV semiconductors.

Abstract: A method includes providing a substrate having an n-type fin-like field-effect transistor (NFET) region and forming a fin structure in the NFET region. The fin structure includes a first layer having a first semiconductor material, and a second layer under the first layer and having a second semiconductor material different from the first semiconductor material. The method further includes forming a patterned hard mask to fully expose the fin structure in gate regions of the NFET region and partially expose the fin structure in at least one source/drain (S/D) region of the NFET region. The method further includes oxidizing the fin structure not covered by the patterned hard mask, wherein the second layer is oxidized at a faster rate than the first layer. The method further includes forming an S/D feature over the at least one S/D region of the NFET region.

Abstract: A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a side of the gate stack and connected to the semiconductor fin. The source/drain region includes an inner portion thinner than the semiconductor fin, and an outer portion outside the inner portion. The semiconductor fin and the inner portion of the source/drain region have a same composition of group IV semiconductors.

Abstract: The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with source/drain (S/D) features and a high-k/metal gate (HK/MG). A first HK/MG in a first gate region wraps over an upper portion of a first fin structure, the first fin structure including an epitaxial silicon (Si) layer as its upper portion and an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion, and the substrate as its bottom portion. A second HK/MG in a second gate region, wraps over an upper portion of a second fin structure, the second fin structure including an epitaxial SiGe layer as its upper portion, an epitaxial Si layer as it upper middle portion, an epitaxial SiGe layer as its lower middle portion, and the substrate as its bottom portion.