Patents by Inventor Kai Lee
Kai Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990378Abstract: An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.Type: GrantFiled: March 24, 2023Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Yuan Chen, Jui-Ping Lin, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
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Publication number: 20240153812Abstract: A method for fabricating a semiconductor device includes the steps of first forming a shallow trench isolation (STI) in a substrate, forming a first gate structure on the substrate and adjacent to the STI, forming a first doped region between the first gate structure and the STI, forming a second doped region between the first doped region and the first gate structure, forming a first contact plug on the first doped region, and then forming a second contact plug on the second doped region.Type: ApplicationFiled: December 4, 2022Publication date: May 9, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wen-Kai Lin, Chi-Horn Pai, Sheng-Yuan Hsueh, Kuo-Hsing Lee, Chih-Kai Kang
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Patent number: 11978678Abstract: A display device includes a first substrate, a light-emitting element, a light conversion layer, and a color filter layer. The light-emitting element is disposed on the first substrate. The light conversion layer is disposed on the light-emitting element. In addition, the color filter layer is overlapped the light-emitting element and the light conversion layer.Type: GrantFiled: August 5, 2022Date of Patent: May 7, 2024Assignee: INNOLUX CORPORATIONInventors: Tung-Kai Liu, Tsau-Hua Hsieh, Wei-Cheng Chu, Chun-Hsien Lin, Chandra Lius, Ting-Kai Hung, Kuan-Feng Lee, Ming-Chang Lin, Tzu-Min Yan, Hui-Chieh Wang
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Patent number: 11968856Abstract: Exemplary subpixel structures include a directional light-emitting diode structure characterized by a full-width-half-maximum (FWHM) of emitted light having a divergence angle of less than or about 10°. The subpixel structure further includes a lens positioned a first distance from the light-emitting diode structure, where the lens is shaped to focus the emitted light from the light-emitting diode structure. The subpixel structure still further includes a patterned light absorption barrier positioned a second distance from the lens. The patterned light absorption barrier defines an opening in the barrier, and the focal point of the light focused by the lens is positioned within the opening. The subpixels structures may be incorporated into a pixel structure, and pixel structures may be incorporated into a display that is free of a polarizer layer.Type: GrantFiled: October 4, 2021Date of Patent: April 23, 2024Assignee: Applied Materials, Inc.Inventors: Chung-Chih Wu, Po-Jui Chen, Hoang Yan Lin, Guo-Dong Su, Wei-Kai Lee, Chi-Jui Chang, Wan-Yu Lin, Byung Sung Kwak, Robert Jan Visser
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Publication number: 20240130140Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.Type: ApplicationFiled: December 26, 2023Publication date: April 18, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ting-Hsiang Huang, Yi-Chung Sheng, Sheng-Yuan Hsueh, Kuo-Hsing Lee, Chih-Kai Kang
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Publication number: 20240124528Abstract: The present invention relates to an antagonist of interleukin-17B receptor (IL-17RB) which features interruption of the interaction of IL-17RB and MLK4. The present invention also relates to use of such antagonist for treatment of diseases or disorders associated with IL-17RB activation. Further disclosed is a phosphorylated IL-17RB as a biomarker for predicting prognosis and/or monitoring progression of cancer.Type: ApplicationFiled: December 14, 2021Publication date: April 18, 2024Applicant: Academia SinicaInventors: Wen-Hwa LEE, Heng-Hsiung WU, Chun-Mei HU, Chun-Kai HUANG
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Patent number: 11960790Abstract: A computer implemented method includes detecting user interaction with mixed reality displayed content in a mixed reality system. User focus is determined as a function of the user interaction based on the user interaction using a spatial intent model. A length of time for extending voice engagement with the mixed reality system is modified based on the determined user focus. Detecting user interaction with the displayed content may include tracking eye movements to determine objects in the displayed content at which the user is looking and determining a context of a user dialog during the voice engagement.Type: GrantFiled: May 27, 2021Date of Patent: April 16, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Austin S. Lee, Jonathan Kyle Palmer, Anthony James Ambrus, Mathew J. Lamb, Sheng Kai Tang, Sophie Stellmach
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Patent number: 11960866Abstract: A method and system are provided to construct, from a TensorFlow graph, a common intermediate representation that can be converted to a plurality of compiler intermediate representations (IRs), which enables compiler optimization to be applied efficiently.Type: GrantFiled: February 10, 2022Date of Patent: April 16, 2024Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Jack Lee, Kai-Ting Amy Wang
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Publication number: 20240120812Abstract: An integrated motor and drive assembly is disclosed and includes a housing, a motor and a drive. The housing includes a motor-accommodation portion and a drive-accommodation portion. The drive includes a power board and a control board. The power board is made of a high thermal conductivity substrate and includes a power element and an encoder disposed on the first side, the first side faces the motor, the power board and the motor are stacked along a first direction, and the second side contacts the housing to from a heat-dissipating route. The control board is disposed adjacent to the power board. The control board and the power board are arranged along a second direction perpendicular to the first direction, and the first direction is parallel to an axial direction of the motor. A part of the power board and a part of the control board are directly contacted to form an electrical connection.Type: ApplicationFiled: July 17, 2023Publication date: April 11, 2024Inventors: Chi-Hsiang Kuo, Yi-Yu Lee, Zuo-Ying Wei, Yuan-Kai Liao, Wen-Cheng Hsieh
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Publication number: 20240120207Abstract: A semiconductor package includes a die having a plurality of devices over a first substrate, where the first substrate includes a dopant at a first concentration and the first substrate has a first width along a horizontal direction. The semiconductor package further includes a second substrate fused with the first substrate, where the second substrate includes the dopant at a second concentration greater than the first concentration.Type: ApplicationFiled: February 15, 2023Publication date: April 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lung-Kai Mao, Wen-Hsiung Lu, Pei-Wei Lee, Szu-Hsien Lee, Chieh-Ning Feng
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Patent number: 11956994Abstract: The present disclosure is generally related to 3D imaging capable OLED displays. A light field display comprises an array of 3D light field pixels, each of which comprises an array of corrugated OLED pixels, a metasurface layer disposed adjacent to the array of 3D light field pixels, and a plurality of median layers disposed between the metasurface layer and the corrugated OLED pixels. Each of the corrugated OLED pixels comprises primary or non-primary color subpixels, and produces a different view of an image through the median layers to the metasurface to form a 3D image. The corrugated OLED pixels combined with a cavity effect reduce a divergence of emitted light to enable effective beam direction manipulation by the metasurface. The metasurface having a higher refractive index and a smaller filling factor enables the deflection and direction of the emitted light from the corrugated OLED pixels to be well controlled.Type: GrantFiled: August 10, 2021Date of Patent: April 9, 2024Assignee: Applied Materials, Inc.Inventors: Chung-Chih Wu, Hoang Yan Lin, Guo-Dong Su, Zih-Rou Cyue, Li-Yu Yu, Wei-Kai Lee, Guan-Yu Chen, Chung-Chia Chen, Wan-Yu Lin, Gang Yu, Byung-Sung Kwak, Robert Jan Visser, Chi-Jui Chang
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Publication number: 20240113202Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.Type: ApplicationFiled: December 1, 2023Publication date: April 4, 2024Inventors: Wen-Kai Lin, Bo-Yu Lai, Li Chun Te, Kai-Hsuan Lee, Sai-Hooi Yeong, Tien-I Bao, Wei-Ken Lin
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Publication number: 20240097035Abstract: Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Chen-Ming Lee, I-Wen Wu, Po-Yu Huang, Fu-Kai Yang, Mei-Yun Wang
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Publication number: 20240093786Abstract: A sealing mechanism is provided, including a housing, a groove, and a sealing element. The housing includes a first member and a second member, and the groove is formed between the first and second members. The sealing element is formed in the groove by Low Pressure Molding (LPM) and surrounds at least one of the first and second members.Type: ApplicationFiled: November 16, 2023Publication date: March 21, 2024Inventors: Wei-Kai HSIAO, Yao-Tsung LEE
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Publication number: 20240096985Abstract: Methods and devices including an air gap adjacent a contact element extending to a source/drain feature of a device are described. Some embodiments of the method include depositing a dummy layer, which is subsequently removed to form the air gap. The dummy layer and subsequent air gap may be formed after a SAC dielectric layer such as silicon nitride is formed over an adjacent metal gate structure.Type: ApplicationFiled: November 27, 2023Publication date: March 21, 2024Inventors: I-Wen WU, Chen-Ming LEE, Fu-Kai YANG, Mei-Yun WANG
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Patent number: 11935932Abstract: In an embodiment, a device includes: a gate electrode; a epitaxial source/drain region adjacent the gate electrode; one or more inter-layer dielectric (ILD) layers over the epitaxial source/drain region; a first source/drain contact extending through the ILD layers, the first source/drain contact connected to the epitaxial source/drain region; a contact spacer surrounding the first source/drain contact; and a void disposed between the contact spacer and the ILD layers.Type: GrantFiled: July 21, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Han Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
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Publication number: 20240083526Abstract: Disclosed is a kingpin assembly comprising a receiver housing, a collet sleeve in the receiver housing, a kingpin in the collet, a spring on the kingpin, a retainer cap on the spring, and a plurality of connectors connecting the receiver housing to the retainer cap. In one embodiment, the retainer cap exerts a pressure against the spring which in turn exerts pressure to a top of the king pin pressing the king pin and collet towards a bottom of the receiver housing.Type: ApplicationFiled: September 13, 2023Publication date: March 14, 2024Inventors: Orelous Paul Bousquet, II, Yoon-Kai Lee
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Publication number: 20240077543Abstract: A battery pack includes a group of cells, a current path switch coupled to the group of cells, and a current monitoring system. The current monitoring system includes a signal detection unit, a logic unit and a current path control unit. The signal detection unit is coupled to the group of cells and/or a positive terminal of the battery pack, and used to detect at least one voltage signal of the group of cells and/or of the positive terminal of the battery pack. The logic unit is coupled to the signal detection unit, and used to generate a calculated value of a voltage signal of the at least one voltage signal and generate a logic signal according to the calculated value. The current path control unit is coupled to the logic unit and the current path switch, and used to control the current path switch according to the logic signal.Type: ApplicationFiled: April 10, 2023Publication date: March 7, 2024Applicant: RICHTEK TECHNOLOGY CORP.Inventors: Hsu-Kai Hou, Po-Ching Lee, Tseng-Chuan Wu
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Publication number: 20240075558Abstract: A processing method of a single crystal material includes the following steps. A single crystal material is provided as an object to be modified. The amorphous phase modification apparatus is used for emitting a femtosecond laser beam to process an internal portion of the object to be modified. The processing includes using a femtosecond laser beam to form a plurality of processing lines in the internal portion of the object to be modified, wherein each of the processing lines include a zigzag pattern processing, and a processing line spacing between the plurality of processing lines is in a range of 200 ?m to 600 ?m, wherein after the object to be modified is processed, a modified layer is formed in the object to be modified. Slicing or separating out a portion in the object to be modified that includes the modified layer.Type: ApplicationFiled: August 23, 2023Publication date: March 7, 2024Applicants: GlobalWafers Co., Ltd., mRadian Femto Sources Co., Ltd.Inventors: Chien Chung Lee, Bo-Kai Wang, Shang-Chi Wang, Chia-Chi Tsai, I-Ching Li
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Publication number: 20240079267Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first diffusion barrier layer made of a dielectric material including a metal element, nitrogen, and oxygen and a first protection layer made of a dielectric material including silicon and oxygen and in direct contact with the top surface of the first diffusion barrier layer. The semiconductor device structure also includes a first thickening layer made of a dielectric material including the metal element and oxygen and in direct contact with the top surface of the first protection layer. A maximum metal content in the first thickening layer is greater than that in the first diffusion barrier layer. The semiconductor device structure further includes a conductive feature surrounded by and in direct contact with the first diffusion barrier layer, the first protection layer, and the first thickening layer.Type: ApplicationFiled: November 9, 2023Publication date: March 7, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Cheng SHIH, Tze-Liang LEE, Jen-Hung WANG, Yu-Kai LIN, Su-Jen SUNG