Abstract: A multi-port coupled inductor with interference suppression is provided with a first signal port connected to a first resistor port via a first inductor; a second resistor port connected to the first resistor port via a second inductor; a second signal port connected to the second resistor port via a third inductor; a third resistor port connected to the first resistor port via a first resistor; a fourth resistor port connected to the third resistor port via a fourth inductor and to the second resistor port via a second resistor; a third signal port connected to the third resistor port via a fifth inductor; and a fourth signal port connected to the fourth resistor port via a sixth inductor.

Abstract: An asymmetric signal path approach is used to extract differential signals out of the photodetector (e.g., a photodiode) for amplification by a differential transimpedance amplifier (TIA). This asymmetric-path differential TIA configuration has less low-frequency Inter Symbol Interference (ISI) (also known as Baseline Wander), less high-frequency noise amplification, and higher bandwidth capabilities. There is no power penalty with this design in comparison to a single-ended TIA, can extend the range of the link for a given system power consumption, and can decrease transmitter power for a given range.

Abstract: An apparatus includes a first digital-to-time converter (DTC) and a second DTC. The first DTC includes a sequence of delay stages. Each of the delay stages adds a delay to an input signal based on a control signal. Each delay stage includes a comparator and a capacitor coupled to an input of the comparator and to ground. The second DTC is coupled in parallel to the first DTC. The second DTC adds a delay to the input signal based on a complement of the control signal.

Abstract: An accurate replica oscillator-based frequency tracking loop (FTL) is provided. The replica oscillator used in the FTL can be at a lower frequency and therefore can consume much lower power compared to a main oscillator, such as an injection locked oscillator (ILO). The proposed FTL accurately sets the free running frequency of an ILO across process, voltage and temperature (PVT). Techniques are also provided to compensate the gain and offset error between the replica oscillator and the ILO.

Abstract: A system includes a transimpedance amplifier, disposed on a chip, having a front-end section and a back-end section; an on-chip linear regulator, on the chip, arranged to power the front-end section; and an off-chip switching regulator, off the chip, arranged to power the back-end section. The arrangement provides low noise power supply for the front-end section, while providing a more power efficient switching regulator to power the back-end section. The output voltage of the on-chip linear regulator and the output voltage of the off-chip switching regulator are controlled to be the same.

Abstract: A voltage controlled oscillator (VCO) is described. The VCO includes a plurality of nodes coupled with a plurality of transistors, and a first inductor-capacitor (LC) tank coupled with a second LC tank. The first LC tank and the second LC tank include a shared inductor structure coupled to the plurality of nodes. The first LC tank and the second LC tank each include a capacitor. The capacitors are each coupled on a first side to a node of the plurality of nodes and on a second side to a respective capacitor in the other LC tank. The first LC tank and the second LC tank are configured to resonate at a fundamental frequency for differential-mode signals, and the first LC tank and the second LC tank are configured to resonate at twice the fundamental frequency for common-mode signals.

Abstract: Presented herein are methodologies for generating clock signals for transceivers that rely on frequency and phase error correction functions. The methodology includes generating a differential clock signal at a fundamental frequency, generating, based on the differential clock signal and using a multiphase generator, four quadrature signals at the fundamental frequency, supplying the four quadrature signals to an injection-locked phase rotator, and outputting, from the injection-locked phase rotator, a phase adjusted multiphase clock signal based on the four quadrature signals.

Abstract: A flip-flop is provided that includes an input latch, configured to receive a data signal and a complement and produce set and reset pulses based on a clock and a difference between the data signal and the complement; and an output latch, configured to store a data value in a first memory and a complement data value in a second memory based on the set and reset pulses and the clock. Various buffers configured to invert and amplify the set and reset pulses before provision to the output latch stages are optionally disposed between the input and output latches. The input latch includes two signal arms, two difference transistors (one gate controlled by the clock and the other by a clock complement) coupled oppositely to one another (by respective drains and sources) to the signal arms, and two regeneration inverters coupled oppositely to one another to the signal arms.

Abstract: A flip-flop is provided that includes an input latch, configured to receive a data signal and a complement and produce set and reset pulses based on a clock and a difference between the data signal and the complement; and an output latch, configured to store a data value in a first memory and a complement data value in a second memory based on the set and reset pulses and the clock. Various buffers configured to invert and amplify the set and reset pulses before provision to the output latch stages are optionally disposed between the input and output latches. The input latch includes two signal arms, two difference transistors (one gate controlled by the clock and the other by a clock complement) coupled oppositely to one another (by respective drains and sources) to the signal arms, and two regeneration inverters coupled oppositely to one another to the signal arms.

Abstract: A system includes a transimpedance amplifier, disposed on a chip, having a front-end section and a back-end section; an on-chip linear regulator, on the chip, arranged to power the front-end section; and an off-chip switching regulator, off the chip, arranged to power the back-end section. The arrangement provides low noise power supply for the front-end section, while providing a more power efficient switching regulator to power the back-end section. The output voltage of the on-chip linear regulator and the output voltage of the off-chip switching regulator are controlled to be the same.

Abstract: Presented herein are methodologies for generating clock signals for transceivers that rely on frequency and phase error correction functions. The methodology includes generating a differential clock signal at a fundamental frequency, generating, based on the differential clock signal and using a multiphase generator, four quadrature signals at the fundamental frequency, supplying the four quadrature signals to an injection-locked phase rotator, and outputting, from the injection-locked phase rotator, a phase adjusted multiphase clock signal based on the four quadrature signals.

Abstract: Thermal tuning and quadrature control of opto-electronic devices using active extinction ratio tracking is proved by phase shifting, via a first phase shifter, a first optical signal carried on a first arm of an interferometer relative to a second optical signal carried on a second arm of the interferometer; combining the first optical signal with the second optical signal as an output signal; detecting a peak value in the output signal; and adjusting a relative phase offset imparted by the first phase shifter on the first optical signal relative to the second optical signal, based on the peak value, to increase an amplitude of the peak value. In various embodiments, the peak value is increased over time to maximize an extinction ratio of the optoelectronic device and maintain the extinction ratio in a maximized state during operation.

Abstract: A driver circuit for a Mach-Zehnder modulator is provided that includes a first driver having an input to receive one of an input data or input data complement, and an output to be coupled to a first application voltage node associated with a first arm of a Mach-Zehnder modulator. The driver circuit includes a second driver having an input to receive the other of the input data complement or input data, and an output to be coupled to a second application voltage node associated with the first arm of the Mach-Zehnder modulator. The first driver and the second driver differentially drive the first and second application voltage nodes associated with the first arm of the Mach-Zehnder modulator to result in a voltage swing associated with a voltage applied to the first arm that is twice the supply voltage.

Abstract: In one embodiment, stable and controlled circuit element biasing is provided in a circuit comprising a voltage source operable to output a first voltage, a reference voltage source operable to output a reference voltage, a circuit element biased, during operation, by the first voltage at a first end and by a second voltage at a second end, a voltage controller coupled to the second end of the circuit element, wherein the voltage controller is operable to adjust the second voltage based on a gain output, a gain controller operable to receive the reference voltage as a first input and the second voltage as a second input, wherein the gain controller is operable to generate, at an output of the gain controller, the gain output based on the second voltage and the reference voltage, and a feedback loop that extends from the output of the gain controller, through the voltage controller, and to the second input.

Abstract: A circuit includes a front end section configured to receive input current signals; a programmable gain amplifier section coupled to the front end section, the programmable gain amplifier section including a plurality of inverters connected in series without a resistor disposed therebetween; and an output buffer section coupled to the programmable gain amplifier section and configured to output voltage signals.

Abstract: A driver circuit for a Mach-Zehnder modulator is provided that includes a first driver having an input to receive one of an input data or input data complement, and an output to be coupled to a first application voltage node associated with a first arm of a Mach-Zehnder modulator. The driver circuit includes a second driver having an input to receive the other of the input data complement or input data, and an output to be coupled to a second application voltage node associated with the first arm of the Mach-Zehnder modulator. The first driver and the second driver differentially drive the first and second application voltage nodes associated with the first arm of the Mach-Zehnder modulator to result in a voltage swing associated with a voltage applied to the first arm that is twice the supply voltage.

Abstract: A circuit includes a front end section configured to receive input current signals; a programmable gain amplifier section coupled to the front end section, the programmable gain amplifier section including a plurality of inverters connected in series without a resistor disposed therebetween; and an output buffer section coupled to the programmable gain amplifier section and configured to output voltage signals.

Abstract: A circuit includes a front end section configured to receive input current signals; a programmable gain amplifier section coupled to the front end section, the programmable gain amplifier section including a plurality of inverters connected in series without a resistor disposed therebetween; and an output buffer section coupled to the programmable gain amplifier section and configured to output voltage signals.

Abstract: A circuit includes a front end section configured to receive input current signals; a programmable gain amplifier section coupled to the front end section, the programmable gain amplifier section including a plurality of inverters connected in series without a resistor disposed therebetween; and an output buffer section coupled to the programmable gain amplifier section and configured to output voltage signals.

Abstract: Embodiments herein describe a reference-less CDR circuit that receives electrical signals that may have been transmitted along either an electrical or optical interconnect which are then processed to identify the original data. To do so, the CDR circuit includes a frequency locking loop (FLL) and a phase locking loop (PLL) which generate control signals for a voltage controlled oscillator (VCO). In one embodiment, the FLL generates a coarse adjustment signal which the VCO uses to output a recovered clock that substantially matches the frequency of the received electrical signal. The PLL, on the other hand, generates a fine adjustment signal which the VCO uses to make small adjustments (e.g., half cycle phase shifts) to the recovered clock. The recovered clock outputted by the VCO is then fed back and used as an input in both the FLL and the PLL.