Abstract: A display device, which includes a plurality of pixels; a data driver for outputting data signals to the pixels; a bias current outputting unit for outputting a bias current having a predetermined magnitude; a plurality of driving current outputting units for outputting driving currents to the pixels; and a first switch connected between the bias current outputting unit and the driving current outputting units for selecting one of the driving current outputting units to connect to the bias current outputting unit, wherein the magnitudes of the driving currents are substantially the same as a magnitude of the bias current.

Abstract: A semiconductor memory apparatus includes: a first bit line of to a first memory bank; a first middle input/output line configured to be electrically connected to the first bit line; a second bit line of a second memory bank; a second middle input/output line configured to be electrically connected to the second bit line; and a shared local input/output line configured to be electrically connected to the first and second middle input/output lines. A bank selection signal controls both the electrical connection between the shared local input/output line and the first middle input/output line and the electrical connection between the shared local input/output line and the second middle input/output line.

Abstract: A flash memory using hot carrier injection and a method of operating the same are provided. A plurality of strings constituting a page are formed on a single p-well and share the p-well. During a program operation, a string selection transistor is turned off, and electrons are accumulated in a source or drain region in response to a bias voltage applied to the p-well. Thereafter, the accumulated electrons are trapped in a charge trap layer of a memory cell in response to a program voltage applied through a word line. Also, during an erase operation, holes accumulated in response to a bias voltage applied to the p-well are trapped in the charge trap layer in response to an erase voltage. The flash memory performs NAND-type program and erase operations using hot carrier injection.

Abstract: A semiconductor memory apparatus includes: a first bit line of to a first memory bank; a first middle input/output line configured to be electrically connected to the first bit line; a second bit line of a second memory bank; a second middle input/output line configured to be electrically connected to the second bit line; and a shared local input/output line configured to be electrically connected to the first and second middle input/output lines. A bank selection signal controls both the electrical connection between the shared local input/output line and the first middle input/output line and the electrical connection between the shared local input/output line and the second middle input/output line.

Abstract: A flash memory using hot carrier injection and a method of operating the same are provided. A plurality of strings constituting a page are formed on a single p-well and share the p-well. During a program operation, a string selection transistor is turned off, and electrons are accumulated in a source or drain region in response to a bias voltage applied to the p-well. Thereafter, the accumulated electrons are trapped in a charge trap layer of a memory cell in response to a program voltage applied through a word line. Also, during an erase operation, holes accumulated in response to a bias voltage applied to the p-well are trapped in the charge trap layer in response to an erase voltage. The flash memory performs NAND-type program and erase operations using hot carrier injection.

Abstract: A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.

Abstract: A semiconductor memory apparatus includes: a first bit line of to a first memory bank; a first middle input/output line configured to be electrically connected to the first bit line; a second bit line of a second memory bank; a second middle input/output line configured to be electrically connected to the second bit line; and a shared local input/output line configured to be electrically connected to the first and second middle input/output lines. A bank selection signal controls both the electrical connection between the shared local input/output line and the first middle input/output line and the electrical connection between the shared local input/output line and the second middle input/output line.

Abstract: A main decoding circuit includes a shared column selection signal generating unit and a switching unit. The shared column selection signal generating unit receives a column decoding signal to generate a shared column selection signal. The switching unit selectively provides the shared column selection signal to one of a column selection line of a first memory bank and a column selection line of a second memory bank in response to a bank selection signal.

Abstract: A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.

Abstract: An on-die thermal sensor includes an integrating analog-digital converter not requiring a negative reference voltage input. The on die thermal sensor includes a band gap unit, an integrating unit and a counting unit. The band gap unit senses a temperature to output a first voltage corresponding to the sensed temperature. The integrating unit integrates a difference between a reference voltage and a comparing voltage to output a second voltage wherein the comparing voltage has a voltage level higher than that of the reference voltage. The counting unit counts clocks of a clock signal input thereto until the second voltage reaches the first voltage, thereby outputting a thermal code corresponding to the voltage level of the first voltage.

Abstract: A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.

Abstract: A charge pump for a DC-DC converter includes an input terminal receiving an input voltage, an output terminal outputting an output voltage, a plurality of charge pumping stages connected in series between the input terminal and the output terminal, and a voltage level shifter shifting voltage levels of first and second gate clock signals so that received first and second gate clock signals have a predetermined amplitude. Therefore, the charge pump can increase power efficiency by maximizing a magnitude of VGS. A DC-DC converter using the charge pump can also be applied to a portable device, for minimizing power consumption, and a method for improving power efficiency of the DC-DC converter is provided.

Abstract: A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.

Abstract: Provided may be a gate pattern, flash memory and methods of manufacturing and operating the same. A gate pattern may include a floating gate on a tunneling dielectric layer, an inter-gate dielectric layer on the floating gate, a first control gate on the inter-gate dielectric layer, and a second control gate on the inter-gate dielectric layer and spaced apart from the first control gate. Each of the control gates sets four states according to an application time of a program voltage applied to the control gates. Thus, one control gate may program 2-bit data.

Abstract: A clock driver is provided. A first driving unit is configured with a plurality of drivers and receives a first clock signal to drive a first pumping clock. A second driving unit is configured with a plurality of drivers and receives a second clock signal to drive a second pumping clock. A charge recycling switch is connected between an output terminal of the first driving unit and an output terminal of the second driving unit. A switch controller selectively transfers an input clock signal of the first or second driving unit to the charge recycling switch in response to the first and second pumping clock signals.

Abstract: An on-die thermal sensor includes an integrating analog-digital converter not requiring a negative reference voltage input. The on die thermal sensor includes a band gap unit, an integrating unit and a counting unit. The band gap unit senses a temperature to output a first voltage corresponding to the sensed temperature. The integrating unit integrates a difference between a reference voltage and a comparing voltage to output a second voltage wherein the comparing voltage has a voltage level higher than that of the reference voltage. The counting unit counts clocks of a clock signal input thereto until the second voltage reaches the first voltage, thereby outputting a thermal code corresponding to the voltage level of the first voltage.

Abstract: A display apparatus includes a display panel; a light source unit including a plurality of first point light sources and a plurality of second point light sources, wherein the point light sources supply light to the display panel; an optical film including a plurality of openings, wherein each opening exposes a first point light source, and is provided between the display panel and the light source unit at a distance from the light source unit; and a light source driver which supplies a driving power to the first point light sources if a three-dimensional image is displayed on the display panel, and supplies the driving power to the second point light sources if a two-dimensional image is displayed on the display panel.

Abstract: A clock driver is provided. A first driving unit is configured with a plurality of drivers and receives a first clock signal to drive a first pumping clock. A second driving unit is configured with a plurality of drivers and receives a second clock signal to drive a second pumping clock. A charge recycling switch is connected between an output terminal of the first driving unit and an output terminal of the second driving unit. A switch controller selectively transfers an input clock signal of the first or second driving unit to the charge recycling switch in response to the first and second pumping clock signals.

Abstract: A display device, which includes a plurality of pixels; a data driver for outputting data signals to the pixels; a bias current outputting unit for outputting a bias current having a predetermined magnitude; a plurality of driving current outputting units for outputting driving currents to the pixels; and a first switch connected between the bias current outputting unit and the driving current outputting units for selecting one of the driving current outputting units to connect to the bias current outputting unit, wherein the magnitudes of the driving currents are substantially the same as a magnitude of the bias current.

Abstract: A charge pump for a DC-DC converter includes an input terminal receiving an input voltage, an output terminal outputting an output voltage, a plurality of charge pumping stages connected in series between the input terminal and the output terminal, and a voltage level shifter shifting voltage levels of first and second gate clock signals so that received first and second gate clock signals have a predetermined amplitude. Therefore, the charge pump can increase power efficiency by maximizing a magnitude of VGS. A DC-DC converter using the charge pump can also be applied to a portable device, for minimizing power consumption, and a method for improving power efficiency of the DC-DC converter is provided.