SEMICONDUCTOR MEMORY APPARATUS AND DATA INPUT/OUTPUT METHOD THEREOF
A semiconductor memory apparatus includes: a first bit line of to a first memory bank; a first middle input/output line configured to be electrically connected to the first bit line; a second bit line of a second memory bank; a second middle input/output line configured to be electrically connected to the second bit line; and a shared local input/output line configured to be electrically connected to the first and second middle input/output lines. A bank selection signal controls both the electrical connection between the shared local input/output line and the first middle input/output line and the electrical connection between the shared local input/output line and the second middle input/output line.
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The present application claims priority to Korean application number 10-2009-0096881, filed on Oct. 12, 2009, which is incorporated by reference in its entirety as set forth in full.
BACKGROUND OF THE INVENTION1. Technical Field
Embodiments of the present invention relate generally to a semiconductor technology, and more particularly, to a semiconductor memory apparatus and a data input/output method thereof.
2. Related Art
To obtain high-speed operation of semiconductor memory, a plurality of stacked memory banks constituting a stacked bank structure is being employed in the semiconductor memory apparatus to improve data access time. In a semiconductor memory apparatus having the stacked bank structure, memory cell regions are partitioned into a plurality of memory blocks, and each of the partitioned memory blocks comprises a plurality of stacked memory banks.
The first column decoder 11 and the first input/output driver perform a data read or write (hereinafter, referred to as ‘read/write’) operation on the first memory bank Bank1, and the second column decoder 12 and the second input/output driver 22 perform a data read/write operation on the second memory bank Bank2. More specifically, in the data read/write operation on the first memory bank Bank1, the first column decoder 11 generates, in response to column address signal ‘Ya<2:7, 9> and a strobe signal ‘strobe<0>, a column selection signal ‘Yi_up’ to enable a column selection line ‘CSL_up’ of the first memory bank Bank1. In the data read/write operation on the second memory bank Bank2, the second column decoder 12 generates, in response to the column address signals ‘Ya<2:7, 9> and a strobe signal ‘strobe<1>, a column selection signal ‘Yi_dn’ to enable a column selection line ‘CSL_dn’ of the second memory bank Bank2. As shown in
Thus, as is shown in
The requirement of separate column decoders and input/output drivers makes it difficult to secure a lay-out margin of the semiconductor memory apparatus. A technique in which stacked memory banks share a column selection line has been proposed, but the technique causes an overload on the column decoder facing the column selection line. In addition, no proper technique that allows the stacked memory banks to share the input/output driver has been proposed until now.
SUMMARY OF THE INVENTIONEmbodiments of the present invention include a semiconductor memory apparatus and a data input/output method thereof, in which a plurality of stacked memory banks can share a column decoder and an input/output driver.
In one embodiment of the present invention, a semiconductor memory apparatus includes: a first bit line of a first memory bank; a first middle input/output line configured to be electrically connected to the first bit line; a second bit line of a second memory bank; a second middle input/output line configured to be electrically connected to the second bit line; and a shared local input/output line configured to be electrically connected to the first and second middle input/output lines, wherein a bank selection signal controls both the electrical connection between the shared local input/output line and the first middle input/output line and the electrical connection between the shared local input/output line and the second middle input/output line.
In another embodiment of the present invention, a semiconductor memory apparatus includes: a shared column decoding unit configured to simultaneously enable a column selection line of the first and second memory banks in response to a column address signal and a main strobe signal; an input/output switching unit configured to selectively and electrically connect the first and second memory banks to a shared local input/output line in response to a bank selection signal; and a shared input/output driving unit configured to amplify data transferred via the shared local input/output line to transfer the amplified data onto a global input/output line in a data read operation, and amplify data transferred via the global input/output line to transfer the amplified data onto the shared local input/output line in a data write operation, in response to the main strobe signal.
In still another embodiment of the present invention, a semiconductor memory apparatus includes: a first memory bank; a second memory bank; first and second middle input/output lines configured to communicate with the first and second memory banks in response to a column selection signal, respectively; and a shared local input/output line configured to be electrically connected to the first and second middle input/output lines, wherein the column selection signal of the first and second memory banks is configured to be simultaneously enabled, and the electrical connection between the shared local input/output line and the first memory bank and the electrical connection between the shared local input/output line and the second memory bank are selectively made in response to a bank selection signal.
In still another embodiment of the present invention, a data input/output method of a semiconductor memory apparatus includes: enabling both of the column selection signals of the first and second memory banks when a data read/write operation is performed on the first memory bank and when the data read/write operation is performed on the second memory bank; and selectively and electrically connecting the first and second memory banks, on which the data read/write operation is to be actually performed, to a shared local input/output line.
Features, aspects, and embodiments are described in conjunction with the attached drawings, in which;
Hereinafter, a semiconductor memory apparatus and a data input/output method thereof, according to the present invention, will be described below with reference to the accompanying drawings through preferred embodiments.
Hereinafter, it is assumed that the first and second memory banks Bank1 and Bank2 of semiconductor memory apparatus 1 constitute the stacked bank structure. Since, in general, both a same global input/output line and a same input/output pad are assigned to a plurality of memory banks constituting the stacked bank structure, both a same global input/output line GIO and a same input/output pad DQ are assigned to the first and second memory banks Bank1 and Bank2 in
The first and second memory banks Bank1 and Bank2 share a column selection line CSL and local input/output lines LIO and LIOB. The column selection line CSL is included for selection of a column of the semiconductor memory apparatus 1. A column selection signal ‘Yi’ generated from the column decoding unit 100 is provided via the column selection line CSL. The local input/output lines LIO and LIOB are data input/output lines which selectively transfer data stored in the first memory bank Bank1 and data stored in the second memory bank Bank2 onto the global input/output line GIO, in a data read operation; and selectively transfer data transferred via the global input/output line GIO to the first memory bank Bank1 and to the second memory bank Bank2, in a data write operation. The semiconductor memory apparatus 1 includes a number of the column selection lines CSL and a number of the local input/output lines LIO and LIOB as much as the number of columns of the first and second memory banks Bank1 and Bank2.
Referring back to
However, in
The shared input/output driving unit 200 performs the data read/write operation in response to the main strobe signal ‘mstrobe’. More specifically, for a data read operation on the first memory bank Bank1 and for a data read operation on the second memory bank Bank2, in response to the main strobe signal ‘mstrobe’, the shared input/output driving unit 200 receives and amplifies data on the shared local input/output lines LIO and LIOB and transfers the amplified data onto the global input/output line GIO. On the other hand, for the data write operation on the first memory bank Bank1 and for the data write operation on the second memory bank Bank2, in response to the main strobe signal ‘mstrobe’, the shared input/output driving unit 200 amplifies the data on the global input/output line GIO and transfers the amplified data onto the shared local input/output lines LIO and LIOB. That is, in response to the main strobe signal ‘mstrobe’, the shared input/output driving unit 200 is enabled and performs the amplification operation, both when the semiconductor memory apparatus 1 performs the data read/write operation on the first memory bank Bank1 and when the semiconductor memory apparatus 1 performs the data read/write operation on the second memory bank Bank2. In an embodiment, the shared input/output driving unit 200 comprises a plurality of input/output drivers, as will be described in further detail later. Since the first and second memory banks Bank1 and Bank2 share the local input/output lines LIO and LIOB, the number of the input/output drivers can be reduced to half the number of the input/output drivers of the conventional art.
The shared local input/output lines LIO and LIOB are selectively and electrically connected to the first memory bank Bank1 and the second memory bank Bank2 in response to the bank selection signals ‘Liorst_up’ and ‘Liorst_dn’. More specifically, when the bank selection signals ‘Liorst_up’ and ‘Liorst_dn’ are such that the first memory bank Bank1 is selected, the shared local input/output lines LIO and LIOB communicate with only the first memory bank Bank1. On the other hand, when the bank selection signals ‘Liorst_up’ and ‘Liorst_dn’ are such that the second memory bank Bank2 is selected, the shared local input/output lines LIO and LIOB communicate with only the second memory bank Bank2. Therefore, the interval during which the shared local input/output lines LIO and LIOB are electrically connected to the first memory bank Bank1 does not overlap with the interval during which the shared local input/output lines LIO and LIOB are electrically connected to the second memory bank Bank2.
As such, even though the first and second memory banks Bank1 and Bank2 share the column decoding unit and the input/output driving unit, the semiconductor memory apparatus 1 according to the embodiment can properly perform data read/write operations without a data collision. This is because the shared local input/output lines LIO and LIOB selectively communicate with the first and second memory banks Bank1 and Bank2 in response to the bank selection signals ‘Liorst_up’ and ‘Liorst_dn’.
As shown in
In
As shown in
The shared local input/output lines LIO and LIOB are coupled to the shared input/output driver 210, and an output of the shared input/output driver 210 is coupled to the global input/output line GIO.
Accordingly, both when the semiconductor memory apparatus 1 performs a data read/write operation on the first memory bank Bank1 and when the semiconductor memory apparatus 1 performs a data read/write operation on the second memory bank Bank2, the first and second bit lines BL_up, BLB_up, BL_dn and BLB_dn are electrically connected to the first to fourth middle input/output lines MIO1 to MIO4 and MIO1B to MIO4B, respectively, because the column selection signal ‘Yi’ is enabled irrespective of which memory bank Bank1 or Bank2 the read/write operation is associated with.
When the semiconductor memory apparatus 1 performs the data read/write operation on the first memory bank Bank1, the up bank selection signal ‘Liorst_up’ is enabled, and subsequently the first and second input/output switching units IOSW1 and IOSW2 are both turned on, and on the other hand, the third and fourth input/output switching units IOSW3 and IOSW4 are both turned off. Therefore, the first and second middle input/output lines MIO1, MIO1B, MIO2 and MIO2B are electrically connected to the shared local input/output lines LIO and LIOB, and on the other hand, the third and fourth middle input/output lines MIO3, MIO3B, MIO4 and MIO4B are electrically disconnected from the shared local input/output lines LIO and LIOB. Therefore, even though each of the first to fourth column switches CSW1 to CSW4 of the memory banks Bank1 and Bank2 are turned on in response to the column selection signal ‘Yi’ generated by the column decoding unit 100, whereby the first and second bit lines BL_up, BLB_up, BL_dn and BLB_dn are electrically connected to the first to fourth middle input/output lines MIO1 to MIO4 and MIO1B to MIO4B, the shared local input/output lines LIO and LIOB are electrically connected to only the first and second middle input/output lines MIO1, MIO1B, MIO2 and MIO2B via the first and second input/output switching units IOSW1 and IOSW 2 among the first to fourth middle input/output lines MIO1 to MIO4 and MIO1B to MIO4B. Accordingly, the semiconductor memory apparatus 1 can perform the data read/write operation on the first memory bank Bank1 successfully.
Conversely, when the semiconductor memory apparatus 1 performs the data read/write operation on the second memory bank Bank2, the down bank selection signal ‘Liorst_dn’ is enabled, and subsequently the first and second input/output switching units IOSW1 and IOSW2 are both turned off, and on the other hand, the third and fourth input/output switching units IOSW3 and IOSW4 are both turned on. Therefore, the first and second middle input/output lines MIO1, MIO1B, MIO2 and MIO2B are electrically disconnected from the shared local input/output lines LIO and LIOB, and on the other hand, the third and fourth middle input/output lines MIO3, MIO3B, MIO4 and MIO4B are electrically connected to the shared local input/output lines LIO and LIOB. Therefore, even though each of the first to fourth column switches CSW1 to CSW4 of the memory banks Bank1 and Bank2 are turned on in response to the column selection signal ‘Yi’ generated by the column decoding unit 100, whereby the first and second bit lines BL_up, BLB_up, BL_dn and BLB_dn are electrically connected to the first to fourth middle input/output lines MIO1 to MIO4 and MIO1B to MIO4B, the shared local input/output lines LIO and LIOB are electrically connected to only the third and fourth middle input/output lines MIO3, MIO3B, MIO4 and MIO4B among the first to fourth middle input/output lines MIO1 to MIO4 and MIO1B to MIO4B via the third and fourth input/output switching units IOSW3 and IOSW4. Accordingly, the semiconductor memory apparatus 1 can perform the data read/write operation on the second memory bank Bank2 successfully.
Herein, it is preferable that the respective pulse widths of the bank selection signals ‘Liorst_up’ and ‘Liorst_dn’ are wider than the pulse width of the column selection signal ‘Yi’. More specifically, it is preferable that the respective bank selection signals ‘Liorst_up’ and ‘Liorst_dn’ are enabled earlier than the column selection signal ‘Yi’ and are disabled later than the column selection signal ‘Yi’. When a data read/write operation performed on the first memory bank Bank1 of the semiconductor memory apparatus 1, early enablement of the up bank selection signal ‘Liorst_up’ with respect to the column selection signal ‘Yi’ allows the semiconductor memory apparatus 1 to turn on the first and second input/output switching units IOSW1 and IOSW2 earlier than the corresponding column switches CSW1 and CSW2 and be ready to perform the data read/write operation. Further, late disablement of the up bank selection signal ‘Liorst_up’ with respect to the column selection signal ‘Yi’ allows the semiconductor memory apparatus 1 to substantially maintain the turn-on state of the first and second input/output switching units IOSW1 and IOSW2 until the data read/write operation is finished, thereby allowing the data read/write operation to be completed safely. Likewise, when a data read/write operation is performed on the second memory bank Bank2 of the semiconductor memory apparatus 1, early enablement of the down bank selection signal ‘Liorst_dn’ with respect to the column selection signal ‘Yi’ allows the semiconductor memory apparatus 1 to turn on the third and fourth input/output switching units IOSW3 and IOSW4 earlier than the corresponding column switches CSW3 and CSW4 and be ready to perform the data read/write operation. Further, late disablement of the down bank selection signal ‘Liorst_dn’ with respect to the column selection signal ‘Yi’ allows the semiconductor memory apparatus 1 to substantially maintain the turn-on state of the third and fourth input/output switching units IOSW3 and IOSW4 until the data read/write operation is finished, thereby allowing the data read/write operation to be completed safely.
Referring to
Referring to
As shown in
The first strobe signal generating unit 331 receives delay signals ‘T2b’ and ‘T3b’ and generates the first strobe signal ‘strobe<0>’. In an embodiment, the first strobe signal generating unit 331 includes a first NAND gate ND1 receiving the delay signals ‘T2b’ and ‘T3b’, and first and second inverters IV1 and IV2 sequentially inverting the output of the first NAND gate ND1. Similarly, the second strobe signal generating unit 332 receives delay signals ‘T2′b’ and ‘T3′b’ and generates the second strobe signal ‘strobe<1>’. In an embodiment, the second strobe signal generating unit 332 includes a second NAND gate ND2 receiving the delay signals ‘T2′b’ and ‘T3′b’, and third and fourth inverters IV3 and IV4 sequentially inverting an output of the second NAND gate ND2.
The strobe combination unit 340 combines the first and second strobe signals ‘strobe<0:1>’ to generate the main strobe signal ‘mstrobe’. The strobe combination unit 340 can, in an embodiment, be implemented with an OR gate receiving the first and second strobe signals ‘strobe<0:1>’ to generate the main strobe signal ‘mstrobe’.
In an embodiment, the bank selection signal generating unit 350 includes third and fourth NAND gates ND3 and ND4 and fifth to eighth inverters IV5, IV6, IV7 and IV8. The third NAND gate ND3 receives delay signals ‘T1b’ and ‘T4b’; and therefore, the up bank selection signal ‘Liorst_up’ generated by the bank selection signal generating unit 350 has a pulse width wider than that of the first strobe signal ‘strobe<0>’. Likewise, since the fourth NAND gate ND4 receives delay signals ‘T1′b’ and ‘T4′b’, the down bank selection signal ‘Liorst_dn’ generated from the bank selection signal generating unit 350 has a pulse width wider than that of the second strobe signal ‘strobe<1>’.
It will be apparent to those skilled in the art that the control unit 300 can be implemented in a variety of logic configurations. In addition, it will be understood that the strobe combination unit 340 and the bank selection signal generating unit 350 included in the control unit 300 may alternatively be included in the shared column decoding unit 100 or the shared input/output driving unit 200 or other alternative implementations.
With reference to
In the conventional art, the plurality of stacked memory banks cannot share the local input/output lines, because the conventional semiconductor memory apparatus controls switching units using a signal generated from the active command ‘ACT’, which allows the row address signal ‘Row ADD’ to be inputted to the conventional semiconductor memory apparatus. Herein, if the semiconductor memory apparatus 1 shown in
However, since the semiconductor memory apparatus 1 according to embodiments of the present invention controls the first to fourth input/output switching units IOSW1 to IOSW4 in response to the bank selection signals ‘Liorst_up’ and ‘Liorst_dn’, which are generated from the read/write command ‘RD/WT’, the above-mentioned data collision does not occur. That is, even though the plurality of the stacked memory banks Bank1 and Bank2 share the local input/output lines LIO and LIOB, data collision does not occur because the semiconductor memory apparatus 1 selectively turns on the respective first to fourth input/output switching units IOSW1 to IOSW4 so that the corresponding middle input/output lines are connected during the interval in which the data read/write operation is actually performed rather than during the entire interval of the active mode. Accordingly, in
A data read/write operation of the semiconductor memory apparatus 1 according to an embodiment of the present invention will now be described with reference to
Referring to
Firstly, if the first write command ‘WT’ is applied to the semiconductor memory apparatus 1, the shared column decoding unit 100 enables the column selection signals ‘Yi’ of both the memory banks Bank1 and Bank2 in response to the first pulse signal of the main strobe signal ‘mstrobe’. Therefore, in
Secondly, on the other hand, if the second write command ‘WT’ is applied to the semiconductor memory apparatus 1, the shared column decoding unit 100 enables the column selection signals ‘Yi’ of both the memory banks Bank1 and Bank2 in response to the second pulse signal of the main strobe signal ‘mstrobe’. Therefore, in
Thirdly, if the first read command ‘RD’ is applied to the semiconductor memory apparatus 1, the first bit lines BL_up and BLB_up are electrically connected to the shared local input/output lines LIO and LIOB as described above. Therefore, the shared input/output driving unit 200 amplifies data transferred from the memory cell of the first memory bank Bank1 via the first bit lines BL_up and BLB_up and the shared local input/output lines LIO and LIOB, and outputs the amplified data to outside of the semiconductor memory apparatus 1 via the global input/output line GIO and a pad DQ.
Finally, on the other hand, if the second read command ‘RD’ is applied to the semiconductor memory apparatus 1, the second bit lines BL_dn and BLB_dn are electrically connected to the shared local input/output lines LIO and LIOB as described above. Therefore, the shared input/output driving unit 200 amplifies data transferred from the memory cell of the second memory bank Bank2 via the second bit lines BL_dn and BLB_dn and the shared local input/output lines LIO and LIOB, and outputs the amplified data to outside of the semiconductor memory apparatus 1 via the global input/output line GIO and a pad DQ.
As such, in the semiconductor memory apparatus and the data input/output method thereof according to an embodiment of the present invention, a plurality of stacked memory banks can share a column decoder and an input/output driver without data collision, thereby improving the lay-out margin of the semiconductor memory apparatus.
While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the device and method described herein should not be limited based on the described embodiments. Rather, the apparatus described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.
Claims
1. A semiconductor memory apparatus comprising:
- a first bit line of a first memory bank;
- a first middle input/output line electrically connected to the first bit line;
- a second bit line of a second memory bank;
- a second middle input/output line electrically connected to the second bit line; and
- a shared local input/output line selectively electrically connected to each of the first and second middle input/output lines,
- wherein a bank selection signals control the electrical connection between the shared local input/output line and the first middle input/output line and the electrical connection between the shared local input/output line and the second middle input/output line.
2. The semiconductor memory apparatus of claim 1, wherein the first middle input/output line is electrically connected to the first bit line and the second middle input/output line is electrically connected to the second bit line in response to a column selection signal, such that the first middle input/output line is electrically connected to the first bit line and the second middle input/output line is electrically connected to the second bit line simultaneously.
3. The semiconductor memory apparatus of claim 2, wherein the interval during which the first middle input/output line is electrically connected to the shared local input/output line does not overlapped with the interval during which the second middle input/output line is electrically connected to the shared local input/output line.
4. The semiconductor memory apparatus of claim 1, wherein the bank selection signal includes information indicating which one of the first and second memory banks is associated with a data read/write operation.
5. The semiconductor memory apparatus of claim 1, further comprising a control unit generating the one or more bank selection signals in response to a read/write command and a bank address signal.
6. The semiconductor memory apparatus of claim 2, wherein the bank selection signal is configured to be enabled earlier than the column selection signal, and to be disabled later than the column selection signal.
7. A semiconductor memory apparatus comprising:
- a shared column decoding unit configured to simultaneously enable a column selection line of the first and second memory banks in response to a column address signal and a main strobe signal;
- an input/output switching unit configured to selectively electrically connect the first and second memory banks to a shared local input/output line in response to a bank selection signal; and
- a shared input/output driving unit configured to amplify data transferred via the shared local input/output line and transfer the amplified data onto a global input/output line in a data read operation, and to amplify data transferred via the global input/output line and transfer the amplified data onto the shared local input/output line in a data write operation, in response to the main strobe signal.
8. The semiconductor memory apparatus of claim 7, wherein the bank selection signal includes information indicating which one of the first and second memory banks is associated with the data read/write operation.
9. The semiconductor memory apparatus of claim 7, wherein the main strobe signal includes information on the data read or data write operation of the first and second memory banks.
10. The semiconductor memory apparatus of claim 7, wherein the semiconductor memory apparatus further includes a control unit configured to generate the bank selection signal and the main strobe signal in response to a read/write command and a bank address signal.
11. The semiconductor memory apparatus of claim 7, wherein the bank selection signal is configured to be enabled earlier than a column selection signal, and to be disabled later than the column selection signal.
12. A semiconductor memory apparatus comprising:
- a first memory bank;
- a second memory bank;
- first and second middle input/output lines configured to communicate with the first and second memory banks respectively, in response to a column selection signal; and
- a shared local input/output line selectively electrically connected to the first and second middle input/output lines,
- wherein the column selection signal simultaneously enables communication of the first and second middle input/output lines with the first and second memory banks, and the electrical connection between the shared local input/output line and the first memory bank and the electrical connection between the shared local input/output line and the second memory bank are made selectively in response to a bank selection signal.
13. The semiconductor memory apparatus of claim 12, further comprising a column selection switching unit configured to transfer data stored in the first memory bank onto the first middle input/output line in a data read operation and transfer data transferred via the first middle input/output line to the first memory bank in a data write operation, when the column selection signal is enabled.
14. The semiconductor memory apparatus of claim 12, further comprising a column selection switching unit configured to transfer data stored in the second memory bank onto the second middle input/output line in a data read operation and transfer data transferred via the second middle input/output line to the second memory bank in a data write operation, when the column selection signal is enabled.
15. The semiconductor memory apparatus of claim 12, wherein the bank selection signal includes information indicating which one of the first and second memory banks is associated with a data read/write operation.
16. The semiconductor memory apparatus of claim 12, further comprising a shared input/output driving unit configured to amplify data transferred via the shared local input/output line and transfer the amplified data onto a global input/output line in a data read operation, and to amplify data transferred via the global input/output line and transfer the amplified data onto the shared local input/output line in a data write operation, in response to a main strobe signal.
17. The semiconductor memory apparatus of claim 16, further comprising a control unit configured to generate the bank selection signal and the main strobe signal in response to a read/write command and a bank address signal.
18. A data input/output method of a semiconductor memory apparatus comprising first and second memory banks and a local input/output line shared by the first and second memory banks, the data input/output method comprising:
- enabling a column selection signal of the first memory bank and the second memory bank when a data read/write operation is performed on the first memory bank and also when a data read/write operation is performed on the second memory bank; and
- electrically connecting only one of the first and second memory banks to the shared local input/output line depending upon on which of the first and second memory banks a data read/write operation is to be performed.
19. The data input/output method of claim 18, wherein the column selection signal of the first memory bank and the second memory bank is enabled in response to a main strobe signal and a column address signal.
20. The data input/output method of claim 19, wherein the main strobe signal includes information on the data read/write operation of the first and second memory banks.
21. The data input/output method of claim 18, wherein electrically connecting only one of the first and second memory banks to the shared local input/output line is performed in response to a bank selection signal including information on which one of the first and second memory banks is associated with the data read/write operation.
22. The data input/output method of claim 19, wherein the data input/output method further comprises enabling a shared input/output driving unit coupled to the shared local input/output line in response to the main strobe signal when the data read/write operation is performed on the first memory bank and when the data read/write operation is performed on the second memory bank.
23. The data input/output method of claim 22, further comprising:
- amplifying, by the shared input/output driving unit, data transferred via the shared local input/output line and transferring, by the shared input/output driving unit, the amplified data onto a global input/output line in the data read operation, in response to the main strobe signal; and
- amplifying, by the shared input/output driving unit, data transferred via the global input/output line and transferring, by the shared input/output driving unit the amplified data onto the shared local input/output line in the data write operation, in response to the main strobe signal.
Type: Application
Filed: Dec 31, 2009
Publication Date: Apr 14, 2011
Applicant: HYNIX SEMICONDUCTOR INC. (Gyeonggi-do)
Inventors: Seung Wook KWACK (Ichon-si), Kae Dal KWACK (Ichon-si)
Application Number: 12/650,771
International Classification: G11C 7/00 (20060101); G11C 8/00 (20060101);