Abstract: A touch panel scan system is disclosed for detecting a change in mutual capacitance on the surface of a touch panel. A first touch detect device is provided having a transmitter for transmitting a transmit signal to a select one of a plurality of first lines on a first edge of a touch panel to facilitate a single line scan operation. A second touch detect device is interfaced with a select one or ones of second lines on a second edge of the touch panel having a receiver for receiving therefrom and processing thereof transmit signals coupled thereto from the select one or ones of the first lines to detect changes in a mutual capacitance associated with the select one or ones of the second lines and the first line. At least one of the first or second touch detect devices functions as a master and the other functions as a slave, with the master coupled to the slave and generating a SYNC signal to initiate a single scan operation of a select one of the first lines.

Abstract: An integrated control circuit is disclosed including a central processing unit operating in a normal full system power mode and in a reduced system low power mode, and a memory. A plurality of peripheral units are provided, at least one of which includes an input/output for interfacing with at least an external system for receiving information therefrom and a process block. The process block processes the received information from the external system and during the processing of the received information, data is stored in the at least one peripheral unit, and data is transferred at least to or at least from the memory. The input/output and process blocks are fully operable in the full system power mode and the reduced system power mode. A direct memory access (DMA) transfers data directly between the at least one peripheral and the memory when such data transfer is required by the peripheral.

Abstract: A digital power supply controller is disclosed for controlling the operation of a switched power supply. The controller is contained within an integrated circuit package enclosing an integrated circuit chip. A plurality of inputs are provided on the package for interfacing with the switched power supply for receiving sensed inputs therefrom. A plurality of outputs provide switch control signals for turning on and off switches in the switched power supply. An integrated digital controller on the chip receives the inputs and generates the outputs, and includes an integrated instruction based processing engine for providing a portion of the digital control of the digital controller. A memory associated with the processing engine stores instructions for the processing engine.

Abstract: A touch panel scan system is disclosed for detecting a change in mutual capacitance on the surface of a touch panel. A first touch detect device is provided having a transmitter for transmitting a transmit signal to a select one of a plurality of first lines on a first edge of a touch panel to facilitate a single line scan operation. A second touch detect device is interfaced with a select one or ones of second lines on a second edge of the touch panel having a receiver for receiving therefrom and processing thereof transmit signals coupled thereto from the select one or ones of the first lines to detect changes in a mutual capacitance associated with the select one or ones of the second lines and the first line. At least one of the first or second touch detect devices functions as a master and the other functions as a slave, with the master coupled to the slave and generating a SYNC signal to initiate a single scan operation of a select one of the first lines.

Abstract: A device is provided wherein a traditional EEPROM device is emulated by using two or more pages of block-erasable memory and mapping each traditional EEPROM write instruction to an incremented active data sector in a first page of the block-erasable memory while a second page of the block-erasable memory is being partially or fully erased. Then, when the first page of block-erasable memory has had its plurality of data sectors written, changing the active page to the second block-erasable memory and mapping traditional EEPROM writes to incremented data sectors therein while the previously written block-erasable memory is being partially or fully erased.

Abstract: An apparatus for providing over current protection for a digital pulse width modulator is disclosed. The apparatus includes first logic circuitry for generating a primary interrupt indicating that a detected output current is greater than a threshold current. Second logic circuitry generates a secondary input responsive to the occurrence to the primary interrupt for a predetermined number of times.

Abstract: An apparatus for forcing outputs of a digital controller of a switching power converter to a safe state during shutdown of the switching power converter is described. The apparatus includes a multiplexer providing an output signal of the digital controller and having a first input of the multiplexer connected to receive a switching control signal control signal from the digital controller. The multiplexer also has a plurality of inputs from control registers providing programmed safe state values. The multiplexer connects one of the first input or the inputs from the plurality of control registers to the output of the multiplexer responsive to a multiplexer control signal. Control logic generates the multiplexer control signal responsive to at least one of an end of frame interrupt, an over current interrupt, an enable interrupt or a software bypass signal.

Abstract: A method is disclosed for generating a sequential pattern of motor control instructions under control of a microcontroller for the purpose of controlling a motor. A pattern of motor control instructions is stored in a memory. A timing circuit is operable to generate a periodic output sync signal. The microcontroller is operable to initiate a sequential Read operation of the memory so as to cause sequential reading and output of motor control instructions from the memory in a predetermined order. Each of the read motor control instructions is then stored in a pre-load buffer after output from the memory. The contents of the pre-load buffer is then transferred to an output buffer in synchronization with the output sync signal, wherein the output of motor control instructions from the memory is not required to be periodic.

Abstract: A microcontroller unit having a suspend mode of operation includes a processing circuit for receiving digital information and processing said received digital information. Timing circuitry generates timing signals to the processing circuit responsive to signals received from a clock circuit which generates both an internal clock signal and an external clock signal. Circuitry for controlling the selective application of a synchronized enable signal and the external clock signal to the timing circuitry. The circuitry applies the internal clock signal to the timing circuitry in at least an active mode of operation of the microcontroller unit responsive to at least one first control signal and applies the external clock signal to the timing circuitry in at least a suspend mode of operation of the microcontroller unit responsive to at least one suspend control signal.

Abstract: A distributed power system for delivering DC power to a plurality of loads. A plurality of switching DC/DC converter modules are provided, each disposed proximate one of the loads, and each having associated therewith a switching pulse generator for generating switching pulses. A distributed power line distributes input power to each of the modules and a data communication line distributes command data between the modules, each of the modules uniquely addressable over the data communication line. A timing communication line is also provided for distributing timing information to each of the switching pulse generators. A master controller generates commands and communicates them to the data modules over the data communication line, the master controller operable to generate timing information over the timing communication line to each of the modules for controlling the associated switching pulse generator.

Abstract: A system for controlling a switching power converter and includes a digital controller that receives an analog signal representing the output DC voltage of the power converter for comparison to a desired output voltage level and generates switching control signals to control the operation of the power supply to regulate the output DC voltage to said desired output voltage level. At least two of the switching control signals having a dead time between a first edge of a first control signal and a second edge of a second control signal. The dead time is programmable such that the second edge of the second control signal may occur at a selected point in time either before or after the first edge of the first control signal.

Abstract: A digital power supply controller is disclosed for controlling the operation of a switched power supply. The controller is contained within an integrated circuit package enclosing an integrated circuit chip. A plurality of inputs are provided on the package for interfacing with the switched power supply for receiving sensed inputs therefrom. A plurality of outputs provide switch control signals for turning on and off switches in the switched power supply. An integrated digital controller on the chip receives the inputs and generates the outputs, and includes an integrated instruction based processing engine for providing a portion of the digital control of the digital controller. A memory associated with the processing engine stores instructions for the processing engine.

Abstract: A distributed power system for delivering DC power to a plurality of loads. A plurality of power converter modules having associated therewith a DC/DC power conversion operation are provided, each disposed proximate an associated one of the loads, each of said converter modules having associated therewith a switching pulse generator for generating switching pulses. A distributed power line distributes input power to each of the modules. A data communication line distributes command data between the modules. Each of the modules includes a power regulation section for receiving the input power to generate a DC output by controlling the operation of the switching pulse generator. It also includes a processing section for interfacing with the data communication line for interfacing with the commands, the processing function operating in at least a slave mode to receive commands from the data communication bus. At least one of the modules operates in both a slave mode and a master mode.

Abstract: A digital controller for controlling the operation of a DC-DC switching converter is disclosed. A digital feedback control system is provided for receiving an analog input voltage representing the output of the switching converter and digitally processing the analog input voltage by comparing it to a reference voltage and then determining analog drive signals to control the operation of the switching converter to provide a regulated output. The digital feedback control system operates in accordance with predetermined operating parametrics. The digital feedback control system also has monitoring inputs and control inputs. A microcontroller monitors the operation of the digital feedback control system and is able to change the operating parametrics under certain predetermined conditions.

Abstract: A monolithic digital power supply controller is disclosed for controlling the operation of a switched power supply. The controller is contained within an integrated circuit package enclosing an integrated circuit chip. A plurality of inputs are provided on the package for interfacing with the switched power supply for receiving sensed inputs therefrom. A plurality of outputs provide switch control signals for turning on and off switches in the switched power supply. An integrated digital controller on the chip receives the inputs and generates the outputs, and includes an integrated instruction based processing engine for providing a portion of the digital control of the digital controller. A memory associated with the processing engine stores instructions for the processing engine.

Abstract: A method is disclosed for generating pulse width modulated pulse control signals for controlling switches in a switching power supply. First, a count value is determined of a master clock within a switching cycle of the power supply from beginning to end thereof. A separate state machine providing for each edge in each of pulse control signals and each is operated to generate the associated edge as a function of the sum of a fixed reference count value from the beginning of the switching cycle and a determined count value when the sum is determined to equal the actual count value.

Abstract: A microcontroller unit having a suspend mode of operation includes a processing circuit for receiving digital information and processing said received digital information. Timing circuitry generates timing signals to the processing circuit responsive to signals received from a clock circuit which generates both an internal clock signal and an external clock signal. Circuitry for controlling the selective application of a synchronized enable signal and the external clock signal to the timing circuitry. The circuitry applies the internal clock signal to the timing circuitry in at least an active mode of operation of the microcontroller unit responsive to at least one first control signal and applies the external clock signal to the timing circuitry in at least a suspend mode of operation of the microcontroller unit responsive to at least one suspend control signal.

Abstract: A method is disclosed for generating a sequential pattern of motor control instructions under control of a microcontroller for the purpose of controlling a motor. A pattern of motor control instructions is stored in a memory. A timing circuit is operable to generate a periodic output sync signal. The microcontroller is operable to initiate a sequential Read operation of the memory so as to cause sequential reading and output of motor control instructions from the memory in a predetermined order. Each of the read motor control instructions is then stored in a pre-load buffer after output from the memory. The contents of the pre-load buffer is then transferred to an output buffer in synchronization with the output sync signal, wherein the output of motor control instructions from the memory is not required to be periodic.

Abstract: A digital PID controller for controlling the operation of a switching power converter is disclosed. A data converter is provided for converting the analog sense voltage to a digital sense voltage. A difference circuit then determines the difference between the digital sense voltage and a reference voltage as a digital error voltage, which reference voltage represents a desired output DC voltage for the power converter. A digital compensator processes the digital error voltage. The digital compensator includes a PID compensation network for compensating the digital error signal with a discrete time PID control law and a postprocessing filter for processing the output of the PID compensation network, comprised of a sinc filter with variable parameters to define the operating characteristics thereof, such that a first notch associated therewith can be placed at a desired frequency.

Abstract: An apparatus for providing over current protection for a digital pulse width modulator is disclosed. The apparatus includes first logic circuitry for generating a primary interrupt indicating that a detected output current is greater than a threshold current. Second logic circuitry blanks out current spikes in the output current occurring on a leading pulse edge of at least one of a plurality of outputs of the digital pulse-width modulator.