Patents by Inventor Kafai Leung

Kafai Leung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040246160
    Abstract: Self calibrating SAR analog-to-digital converter. A data converter for converting analog data on a differential data input having a positive analog input terminal and a negative analog input terminal to digital data. The data converter includes a first single ended successive approximation register (SAR) analog-to-digital converter for converting the analog signal on the positive analog input terminal to a first digital signal and a second single ended successive approximation register (SAR) analog-to-digital converter for converting the analog signal on the negative analog input terminal to a second digital signal. A circuit for combining the first and second digital signals as a digital output signal for the data converter that represents the difference between the analog signals on the positive and negative analog input terminals.
    Type: Application
    Filed: June 3, 2003
    Publication date: December 9, 2004
    Inventors: Ka Y. Leung, Kafai Leung
  • Publication number: 20020032571
    Abstract: A data conversion device is provided for storing digital data in a DAT (332) at a 16-bit word length and then recovering the data at a 24-bit word length with an overall reduction in truncation noise that would be inherently associated with data at the 16-bit word length This is facilitated by noise shaping the data at the 16-bit word length prior to storage in the DAT (332) with a noise-shaping filter (324) This results in truncation noise in the lower portion of the frequency band being shifted to the higher portion of the band When the data is recovered, it is converted to a 24-bit word length and then processed through a bandpass filter to filter out the higher frequency noise to yield a signal that has a maximum noise equal to or less than that in the lower portion of the band stored in the DAT (332) Since the truncation noise was shifted from the lower band to the upper band, this is a lower noise level than that inherently associated with the 16-bit word length.
    Type: Application
    Filed: September 25, 1996
    Publication date: March 14, 2002
    Inventors: KA Y. LEUNG, ERIC J. SWANSON, KAFAI LEUNG
  • Patent number: 6356872
    Abstract: A data conversion device is provided for storing digital data in a DAT (332) at a 16-bit word length and then recovering the data at a 24-bit word length with an overall reduction in truncation noise that would be inherently associated with data at the 16-bit word length. This is facilitated by noise shaping the data at the 16-bit word length prior to storage in the DAT (332) with a noise-shaping filter (324). This results in truncation noise in the lower portion of the frequency band being shifted to the higher portion of the band. When the data is recovered, it is converted to a 24-bit word length and then processed through a bandpass filter to filter out the higher frequency noise to yield a signal that has a maximum noise equal to or less than that in the lower portion of the band stored in the DAT (332). Since the truncation noise was shifted from the lower band to the upper band, this is a lower noise level than that inherently associated with the 16-bit word length.
    Type: Grant
    Filed: September 25, 1996
    Date of Patent: March 12, 2002
    Assignee: Crystal Semiconductor Corporation
    Inventors: Ka Yin Leung, Eric J. Swanson, Kafai Leung
  • Patent number: 5777912
    Abstract: A linear phase FIR filter includes a multiplication/accumulator engine which is operable to receive the multi-level data stream and multiply it by predetermined filter coefficients. The coefficients are symmetrical to allow a pre-addition operation wherein the data is first stored in a buffer and then the data for symmetrical coefficients added before multiplication by the coefficient. This results in a reduction of multiplications by a factor of two, thus allowing the multiplication/accumulator engine to operate at one-half the clock rate of the oversampled multi-level data bit stream.
    Type: Grant
    Filed: March 28, 1996
    Date of Patent: July 7, 1998
    Assignee: Crystal Semiconductor Corporation
    Inventors: Ka Yin Leung, Eric J. Swanson, Kafai Leung
  • Patent number: 5652585
    Abstract: An analog-to-digital converter is comprised of an analog delta-sigma modulator (10) and a digital processing section (14). The digital processing section (14) is comprised of a plurality of digital processing sections fabricated on a monolithic device. A high precision FIR filter (20) is provided for providing a high resolution output on a bus (22). Additionally, a low group delay FIR filter (30) is provided to filter the data and provide an output with a much lower delay than that of the FIR filter (20). The output of filter (20) can either be processed through a high-pass filter (40) and/or through a noise shaping psycho-acoustic filter (36) to provide select outputs. These outputs are all input to the serial interface device (52), which is operable to select one of the outputs, that of the filter (30), that of the filter (20), or that of the output of the noise shaping filter (36) or that of the filter (40) for conversion to a serial data stream.
    Type: Grant
    Filed: April 5, 1995
    Date of Patent: July 29, 1997
    Assignee: Crystal Semiconductor Corp.
    Inventors: Ka Yin Leung, Kafai Leung, Eric J. Swanson