Abstract: The present application relates to a digested DDIT4L product as a diagnostic marker for Alzheimer's disease, and use thereof in diagnosing Alzheimer's disease. In particular, the present application relates to use of a substance for detecting a digested intron retention (DIR) product encoding DNA-damage-inducible transcript 4 like (DDIT4L) in a sample of a subject in preparing a product for diagnosing Alzheimer's disease or a mild cognitive disorder and/or assessing (e.g., grading or staging) cognitive disorder progression, a related product thereof, and a method for screening a medicament using the DIR product.

Abstract: The present disclosure provides a semiconductor structure and substrate thereof, and a method for manufacturing the same. In the method for manufacturing the substrate, at least one of groove is provided in each unit sub-region on a surface of a premanufactured substrate, and the premanufactured substrate includes at least one unit region, each of the at least one unit region includes at least two unit sub-regions; in one of the at least one unit region, the at least two unit sub-regions respectively have different porosities, the premanufactured substrate is annealed to form a substrate, wherein openings of the grooves are healed to form self-healing layers, and the grooves that are not fully healed form gaps. When a susceptor transfers heat to the substrate, the unit sub-regions with different porosities respectively have different heat conduction efficiencies.

Abstract: A method and a system for automatic machine learning-based prediction of new energy power with cloud-edge collaboration are disclosed. The method includes: obtaining, in response to a power prediction demand for a target new energy station, future numerical weather prediction data of the target new energy station in a future period and historical output power of a historical period corresponding to the future period; selecting, based on missing of the future numerical weather prediction data and a data amount of the historical output power, a target power prediction model corresponding to the target new energy station; and adjusting the target power prediction model according to the target working mode, and predicting, by the adjusted target power prediction model, a target output power of the target new energy station in the future period, based on the future numerical weather prediction data and the historical output power.

Abstract: Disclosed are a light-emitting device structure and a preparation method therefor. The light-emitting device structure includes a buffer layer, where a material of the buffer layer is a transparent material; and a light-emitting structure disposed on a side of the buffer layer, where the light-emitting structure includes at least one light-emitting unit; where the buffer layer includes at least one microlens structure, the microlens structure includes at least two sub-layers, and each the light-emitting unit corresponds to at least one microlens structure. In the present disclosure, the buffer layer of the transparent material is utilized to manufacture the the microlens structure. On the one hand, a problem of total reflection is alleviated and light extraction efficiency of the light-emitting device is improved. On the other hand, no additional microlens structures is required, thereby reducing production cost.

Abstract: Provided are a semiconductor structure and a semiconductor structure preparation method. The semiconductor structure includes a substrate, a first reflector structure, a second reflector structure, and a light-emitting structure. The substrate includes a first region, a second region, and a third region disposed between the first region and the second region. The first reflector structure is disposed in the first region of the substrate. The second reflector structure is disposed in the second region of the substrate and disposed on the same side of the substrate as the first reflector structure. The light-emitting structure is disposed in the third region of the substrate and disposed on the same side of the substrate as the first reflector structure. Each of the reflective surface of the first reflector structure and the reflective surface of the second reflector structure faces the sidewall of the light-emitting structure.

Abstract: The present disclosure provides a substrate structure, a semiconductor structure, and a method of manufacturing the substrate structures. The substrate structure includes: a base substrate, an insulation layer and a growth substrate on the base substrate in sequence; a groove provided on a side of the base substrate away from the growth substrate, where the groove penetrates at least one part of the base substrate. The present disclosure can improve the heat-dissipation performance of the substrate structure.

Abstract: The present disclosure provides a semiconductor structure and a forming method thereof. The semiconductor structure includes: a substrate and an epitaxial layer disposed on the substrate. At least a part of the epitaxial layer is doped with metal atoms, and the doping concentration of the metal atoms at the bottom surface of the epitaxial layer near the substrate is larger than 1×1017 atoms/cm3.

Abstract: Provided are a full-color LED structure and a preparation method of a full-color LED structure. The full-color LED structure includes a first substrate, first-color light-emitting units, second-color light-emitting units, and third-color light-emitting units. The first-color light-emitting units and the second-color light-emitting units are disposed on a side of the first substrate, disposed in the same layer, and simultaneously prepared. The third-color light-emitting units are disposed on the side of the first-color light-emitting units and the second-color light-emitting units facing away from the first substrate, where a vertical projection of a third-color light-emitting unit on the first substrate does not overlap a vertical projection of a first-color light-emitting unit on the first substrate or a vertical projection of a second-color light-emitting unit on the first substrate.

Abstract: Cleaning tools for cleaning the pull cable of an ingot puller apparatus and methods for cleaning the pull cable are disclosed. The cleaning tool includes a chamber for receiving the pull cable. Pressurized fluid is discharged through one or more nozzles to detach debris from the pull cable. The fluid and debris are collected in an exhaust plenum of the cleaning tool and are expelled through an exhaust tube. The cleaning tool includes one or more guides that guide the cleaning tool in an upper segment of the ingot puller apparatus.

Abstract: A position dependent strain measurement system detected strain as a function of position in an optical sensing fiber using an interferometer having an input coupled to the first end of the optical sensing fiber. An electronic phase measuring sub-system is coupled to an output of the interferometer. The electronic phase measuring sub-system defines a usable optical intensity range of input light of the interferometer, wherein the electronic phase measuring sub-system is capable of measuring the phase of the input light. An optically pumped optical fiber amplifier is coupled between the first end of the optical sensing fiber and the input of the interferometer in series with an electrically pumped semi-conductor optical amplifier. The electrically pumped semi-conductor optical amplifier having a non-linear intensity amplification range that overlaps with the usable optical intensity range.

Abstract: A method includes forming a first conductive feature over a first semiconductor structure; forming a first dielectric layer over the first conductive feature and the first semiconductor structure; removing a portion of the first dielectric layer to expose a top surface of the first conductive feature; forming a second conductive feature over a second semiconductor structure, wherein the first and second conductive features comprise nanotwinned copper; forming a second dielectric layer over the second conductive feature and the second semiconductor structure, wherein the second dielectric layer comprises a same material as the first dielectric layer; removing a portion of the second dielectric layer to expose a top surface of the second conductive feature; and performing a hybrid bonding process to bond the first dielectric layer to the second dielectric layer and bond the first conductive feature to the second conductive feature.

Abstract: A method of manufacturing an electronic device including the following steps is provided herein. A plurality of first electronic components is provided. The plurality of first electronic components is transferred onto a plurality of pickup sites. An empty pickup site from the plurality of pickup sites may be figured out, wherein the plurality of first electronic components is absent at the empty pickup site. A second electronic component is transferred onto the empty pickup site. A target substrate is provided. The plurality of first electronic components and the second electronic component are transferred onto the target substrate.

Abstract: A touch detection system includes a stylus, a panel and a processing circuit. The panel can include a plurality of sensing cells used to receive a first signal and a second signal generated by a touch event. The processing circuit can be coupled to the panel and used to determine a plurality of first areas and a plurality of first intensities corresponding to the first signal, determine a plurality of second areas and a plurality of second intensities corresponding to a second signal, and determine whether the touch event is triggered by the stylus touching the panel according to the first intensities, first areas, the second intensities and the second areas.

Abstract: An electronic device includes a substrate, a spacer, a first element and a second element. The spacer is disposed on the substrate and has a first portion, a second portion, a first opening, a second opening and a third opening arranged in a first direction. In a cross-section view, the second opening is located between the first opening and the third opening, the first portion is located between the first opening and the second opening, and the second portion is located between the second opening and the third opening. A width of the first portion is less than a width of the second portion in the first direction, and an area of the second opening is different from an area of the first opening. The first element is overlapped with the first opening. The second element is overlapped with the third opening.

Abstract: Disclosed is a preparation method for a semiconductor structure. The semiconductor structure includes: a substrate; an epitaxial layer and an epitaxial structure that are stacked on the substrate in sequence. The epitaxial layer is doped with a doping element. In the forming process, a sacrificial layer is formed on the epitaxial layer, and the sacrificial layer is repeatedly etched, such that a concentration of the doping element in the epitaxial layer is lower than a preset value. In this application, the sacrificial layer is formed on the epitaxial layer, and the sacrificial layer is repeatedly etched, such that the concentration of the doping element in the epitaxial layer is lower than the preset value, so as to prevent the doping element in the epitaxial layer from being precipitated upward into an upper-layer structure, ensure the mobility of electrons in a channel layer, and improve the performance of a device.

Abstract: A display device includes a display panel including a plurality of gate lines and a plurality of data lines, the plurality of gate lines intersecting and being insulated with the plurality of data lines, the display panel further including a plurality of sub-pixels arranged in an array, and the plurality of gate lines and the plurality of data lines defining areas where the sub-pixels are located; a gate driver electrically connected to the plurality of gate lines in the display panel; and a source driver bound to the display panel and electrically connected to the plurality of data lines in the display panel, the source driver being configured to set data transmission start time for respective data lines so that effective charging time of respective sub-pixels formed by the plurality of data lines and a same gate line is same.

Abstract: An FPGA-based USB3.0/3.1 control system, including: a USB control module including a USB3.0 control module and/or a USB3.1 control module; a PCS logic module connected to the USB control module via a PIPE interface; an FPGA Serdes serial communication module connected to the PCS logic module; and an external daughter card module connected to the FPGA Serdes serial communication module, wherein the PCS logic module, the FPGA Serdes serial communication module and the external daughter card module are connected in sequence to achieve a port physical layer function for testing the USB 3.0 control module and the USB 3.1 control module. The control system solves the cumbersome problems of incomplete emulation verification, test mode limitations, and unchangeable hardware functions in the prior art.

Abstract: An embodiment semiconductor package includes a package substrate, a first semiconductor die electrically and mechanically coupled to the package substrate, a second semiconductor die electrically and mechanically coupled to the package substrate, a non-conductive film formed between the first semiconductor die and the package substrate, and a capillary underfill material formed between the second semiconductor die and the package substrate. The non-conductive film may be formed in a first region over a surface of the package substrate and the capillary underfill material may be formed over a second region of the surface of the package substrate, such that the second region surrounds the first region in a plan view. The semiconductor package may further include a multi-die frame partially surrounding the first semiconductor die and the second semiconductor die such that a multi-die chip is formed that includes the first semiconductor die, the second semiconductor die, and the multi-die frame.

Abstract: A composite substrate includes a supporting substrate layer, a buried layer and a growth substrate layer stacked in sequence. The buried layer is provided with a plurality of grooves at least partially penetrating the buried layer, the supporting substrate layer includes a charge trapping region beneath the plurality of grooves, and on a plane where the supporting substrate layer is located, shapes of projections of the charge trapping region and a corresponding groove overlap. The charge trapping region is arranged on the supporting substrate layer, and the charge trapping region is used to deplete charges of the supporting substrate layer, so as to increase resistivity of the composite substrate, reducing an impact of crosstalk; and the buried layer is provided with grooves, which may attenuate a stress transmitted from the growth substrate layer to the supporting substrate layer, so as to enhance a mechanical strength of the composite substrate.

Abstract: Disclosed are a semiconductor structure and a manufacturing method for the semiconductor structure. The semiconductor structure includes a light-emitting structure; a light control layer disposed on a side of the light-emitting structure, including a plurality of light control regions regularly arranged and a substrate structure located between the plurality of light control regions; where the plurality of light control regions include a wavelength conversion structure, and the wavelength conversion structure includes a quantum dot and a porous structure adsorbed with the quantum dot. In the present disclosure, the plurality of light control regions and the substrate structure are provided to ensure uniform light output, good directionality, high light extraction rate, and avoidance of light crosstalk in each light control region. The porous structure is utilized to adsorb the quantum dot and achieve a full color display, thereby improving resolution, simplifying a manufacturing process and reducing costs.