Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

Abstract: An interfacial structure, along with methods of forming such, are described. The structure includes a first interfacial layer having a first dielectric layer, a first conductive feature disposed in the first dielectric layer, and a first thermal conductive layer disposed on the first dielectric layer. The structure further includes a second interfacial layer disposed on the first interfacial layer. The second interfacial layer is a mirror image of the first interfacial layer with respect to an interface between the first interfacial layer and the second interfacial layer. The second interfacial layer includes a second thermal conductive layer disposed on the first thermal conductive layer, a second dielectric layer disposed on the second thermal conductive layer, and a second conductive feature disposed in the second dielectric layer.

Abstract: Systems and methods for activating and using dynamic cards are disclosed. In one embodiment, in an information processing apparatus comprising at least one computer processor, a method for activating a dynamic transaction instrument may include: (1) receiving, from an electronic device, an identification of an inactive financial instrument to activate; (2) receiving, from the electronic device, at least one parameter that restricts the use of the inactive financial instrument after it is activated; and (3) activating the inactive financial instrument subject to the at least one parameter by associating, at a backend, an account with the inactive financial instrument.

Abstract: A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.

Abstract: Embodiments of the present disclosure relate to projection stabilization systems and maskless lithography systems having projection stabilization systems. The projection stabilization system compensates for propagating vibrations that move image projection systems (IRS's). The IRS's are in a processing positon prior to operation of the maskless lithography process. One or more stiffeners are coupled to the IPS. The one or more stiffeners apply pressure to flexures coupled to each stiffener. The flexures are coupled to the IPS to provide stabilization to the IPS during the operations of the maskless lithography process. For example, the one or more of stiffeners protect the IPS from vibrations that propagate through the system during operation.

Abstract: A method of making solid oxidesolid oxide electrolyte membrane comprises steps (S1)-(S5). Step (S1), mixing a high molecular polymer and a first solvent to form a first mixed slurry; and homogenizing the first mixed slurry, to obtain a reagent A. Step (S2), mixing an oxide powder, a dispersant and a second solvent to form a second mixed slurry, treating the second mixed slurry, to obtain a reagent B. Step (S3), adding a protective agent into the reagent B to form a third mixed slurry, and homogenizing the third mixed slurry to obtain a reagent C. Step (S4), mixing the reagent A and the reagent C to form a fourth mixed slurry, and treating the fourth mixed slurry a fifth mixed slurry; and homogenizating the fifth mixed slurry to form a solid electrolyte slurry. And step (S5), producing the solid oxidesolid oxide electrolyte membrane by a coating process.

Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.

Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.

Abstract: A fluoride-based resin prepreg and a circuit substrate using the same are provided. The fluoride-based resin prepreg includes 100 PHR of a fluoride-based resin and 20 to 110 PHR of an inorganic filler. Based on a total weight of the fluoride-based resin, the fluoride-based resin includes 10 to 80 wt % of polytetrafluoroethylene (PTFE), 10 to 50 wt % of fluorinated ethylene propylene (FEP), and 0.1 to 40 wt % of perfluoroalkoxy alkane (PFA). The circuit substrate includes a fluoride-based resin substrate and a circuit layer that is formed on the fluoride-based resin substrate.

Abstract: Disclosed are a manual and remote control forward and reverse rotation control device and its control method for DC brushless ceiling fans. The control device includes a power supply, a remote control, a manual control switch assembly and a ceiling fan brushless motor which are electrically connected with one another. A gear position signal can be inputted from a remote end to determine and control the forward and reverse rotations of a brushless motor of the ceiling fan. The remote control can be connected externally by an existing control line or a manual controller module without requiring additional wiring, so as to improve the diversity of structural mechanism, increase the versatility of remote operation, and achieve good functionality and variability of applications.

Abstract: A prepreg and a metallic clad laminate are provided. The prepreg includes a reinforcing material and a thermosetting resin layer. The thermosetting resin layer is formed by immersing the reinforcing material in a thermosetting resin composition. The thermosetting resin composition includes a polyphenylene ether resin, a liquid polybutadiene resin, a crosslinker, and fillers. Based on a total weight of the thermosetting resin composition being 100 phr, an amount of the fillers ranges from 50 phr to 70 phr. The fillers include a granular dielectric filler and a flaky thermal conductive filler. The metallic clad laminate is formed by disposing at least one metal layer onto the prepreg.

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

Abstract: A vital-sign sensor is provided. The vital-sign sensor includes an output/input port, a driving/conversion circuit, a detection circuit, and a controller. The output/input port includes a detection pin. The driving/conversion circuit is coupled to the output/input port and controlled by a control signal. The detection circuit includes an input node coupled to the detection pin. The detection circuit generates a detection signal according to a detection voltage at the input node. In response to the output/input port connecting a sensing probe, the detection voltage has a first voltage value, and the controller detects a type of the sensing probe according to the detection signal corresponding to the first voltage value. The controller generates the control signal according to the determined type. The driving/conversion circuit generates a driving signal according to the control signal to drive the sensing probe.

Abstract: A semiconductor device includes a semiconductor structure, a conductive nitride feature, a third dielectric feature, and a conductive line feature. The semiconductor structure includes a substrate, two source/drain regions disposed in the substrate, a first dielectric feature disposed over the substrate, a gate structure disposed in the first dielectric feature and between the source/drain regions, a second dielectric feature disposed over the first dielectric feature, and a contact feature disposed in the second dielectric feature and being connected to at least one of the source/drain regions and the gate structure. The conductive nitride feature includes metal nitride or alloy nitride, is disposed in the second dielectric feature, and is connected to the contact feature. The third dielectric feature is disposed over the second dielectric feature. The conductive feature is disposed in the third dielectric feature and is connected to the conductive nitride feature opposite to the contact feature.

Abstract: A display panel includes a substrate, a plurality of LEDs, a planarization layer, and a patterned first conductive layer. The plurality of LEDs are on the substrate, each of the plurality of LEDs includes a first electrode facing a front side of the display panel. The planarization layer covers the plurality of LEDs. The first conductive layer is on the planarization layer. The planarization layer defines a plurality of holes, the electrode is exposed by a corresponding hole of the plurality of holes, and the first conductive layer electrical connects to the first electrode through the corresponding hole. The first conductive layer further comprises a trace portion and a plurality of reinforcing portions, each of the plurality of reinforcing portions is aligned with the corresponding hole and is attached to the trace portion. Methods of fabricating the display panel are further disclosed.

Abstract: An application and network analytics platform can capture telemetry from servers and network devices operating within a network. The application and network analytics platform can determine an application dependency map (ADM) for an application executing in the network. Using the ADM, the application and network analytics platform can resolve flows into flowlets of various granularities, and determine baseline metrics for the flowlets. The baseline metrics can include transmission times, processing times, and/or data sizes for the flowlets. The application and network analytics platform can compare new flowlets against the baselines to assess availability, load, latency, and other performance metrics for the application. In some implementations, the application and network analytics platform can automate remediation of unavailability, load, latency, and other application performance issues.

Abstract: A semiconductor structure may include an interposer including on-interposer bump structures, at least one semiconductor die bonded to a first subset of the on-interposer bump structures through first solder material portions, at least one spacer die bonded to a second subset of the on-interposer bump structures through second solder material portions, and a molding compound die frame laterally surrounding each of the at least one semiconductor die and the at least one spacer die. Each of the at least one semiconductor die includes a respective set of transistors and a respective set of metal interconnect structures. Each of the at least one spacer die is free from any transistor therein.

Abstract: An image defect identification method is applied to an image analysis device with an image receiver and an operation processor. The image defect identification method divides a detection image acquired by the image receiver into a plurality of pixel groups, transforms one of the plurality of pixel groups into a distribution curve, compares the distribution curve with a reference curve, and determines an area of the detection image conforming to a specific section of the distribution curve has defect when a difference between the specific section of the distribution curve and a related section of the reference curve is greater than a predefined threshold.

Abstract: An embodiment is an apparatus, such as a plasma chamber. The apparatus includes chamber walls and a chamber window defining an enclosed space. A chamber window is disposed between a plasma antenna and a substrate support. A gas delivery source is mechanically coupled to the chamber window. The gas delivery source comprises a gas injector having a passageway, a window at a first end of the passageway, and a nozzle at a second end of the passageway. The nozzle of the gas delivery source is disposed in the enclosed space. A fastening device is mechanically coupled to the gas delivery source. The fastening device is adjustable to adjust a sealing force against the gas injector.

Abstract: A semiconductor device includes a substrate, a source/drain region disposed in the substrate, a silicide structure disposed on the source/drain region, a first dielectric layer disposed over the substrate, a conductive contact disposed in the first dielectric layer and over the silicide structure, a second dielectric layer disposed over the first dielectric layer, a via contact disposed in the second dielectric layer and connected to the conductive contact, and a first metal surrounding the via contact.