Patents by Inventor Kai-Chiang Wu

Kai-Chiang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Barrier structures between external electrical connectors
    Patent number: 9698079
    Abstract: A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chun Miao, Shih-Wei Liang, Kai-Chiang Wu
  • Packaged Semiconductor Devices and Packaging Methods
    Publication number: 20170186726
    Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a first molding material disposed around the integrated circuit die, and a through-via disposed within the first molding material. A first side of a redistribution layer (RDL) is coupled to the integrated circuit die, the through-via, and the first molding material. A second molding material is over a second side of the RDL, the second side of the RDL being opposite the first side of the RDL. The packaged semiconductor device includes an antenna over the second molding material.
    Type: Application
    Filed: December 29, 2015
    Publication date: June 29, 2017
    Inventors: Tzu-Chun Tang, Chuei-Tang Wang, Chun-Lin Lu, Wei-Ting Chen, Vincent Chen, Shou-Zen Chang, Kai-Chiang Wu
  • Semiconductor Devices and Methods of Manufacture Thereof
    Publication number: 20170162541
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads may be arranged in a ball grid array (BGA), and the may include a plurality of corners. A metal dam is disposed around each of the plurality of corners, such as corners of the BGA.
    Type: Application
    Filed: February 20, 2017
    Publication date: June 8, 2017
    Inventors: Yu-Feng Chen, Kai-Chiang Wu, Chun-Lin Lu, Hung-Jui Ko
  • Barrier structures between external electrical connectors
    Patent number: 9659839
    Abstract: A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chun Miao, Shih-Wei Liang, Kai-Chiang Wu
  • Method of manufacturing package structure
    Patent number: 9661794
    Abstract: A method of manufacturing a package structure includes at least the following steps. A wafer is provided. A flux layer is applied onto at least part of the wafer. A stencil is provided over the wafer. The stencil includes a plurality of apertures exposing the flux layer. A dispenser is provided over the stencil. A plurality of SMDs are fed over the stencil with the dispenser. The dispenser is moved to drive the SMDs into the apertures of the stencil. The stencil is removed and the flux layer is reflowed.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shou-Zen Chang, Chen-Hua Yu, Chung-Shi Liu, Kai-Chiang Wu, Wei-Ting Lin
  • Semiconductor device having a guard ring
    Patent number: 9659879
    Abstract: A semiconductor device includes a semiconductor die having a guard ring disposed in a periphery of the semiconductor die. The semiconductor device also includes a conductive pad over the guard ring. the semiconductor device further has a passivation partially covering the conductive pad, and including a recess to expose a portion of the conductive pad and a post passivation interconnect (PPI) over the passivation. In the semiconductor device, a conductor is extended upwardly from the recess and connected to a portion of the PPI.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 23, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Ching-Feng Yang, Chun-Lin Lu, Kai-Chiang Wu, Vincent Chen
  • Mechanisms for Forming Hybrid Bonding Structures with Elongated Bumps
    Publication number: 20170141073
    Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.
    Type: Application
    Filed: January 30, 2017
    Publication date: May 18, 2017
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Ming-Kai Liu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang, Chia-Chun Miao, Hung-Jen Lin
  • Packaging devices and methods
    Patent number: 9653418
    Abstract: A method of manufacturing a packaging device may include: forming a plurality of through-substrate vias (TSVs) in a substrate, wherein each of the plurality of TSVs has a protruding portion extending away from a major surface of the substrate. A seed layer may be forming over the protruding portions of the plurality of TSVs, and a conductive ball may be coupled to the seed layer and the protruding portion of each of the plurality of TSVs. The seed layer and the protruding portion of each of the plurality of TSVs may extend into an interior region of the conductive ball.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shih-Wei Liang, Kai-Chiang Wu, Ming-Che Ho, Yi-Wen Wu
  • Method for singulating packaged integrated circuits and resulting structures
    Patent number: 9653417
    Abstract: A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through the molding compound and a top portion of the wafer using a beveled saw blade, while leaving a bottom portion of the wafer remaining. The method further includes sawing through the bottom portion of the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the beveled saw blade. The resulting structure is within the scope of the present disclosure.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Ping Wang, Ming-Kai Liu, Kai-Chiang Wu
  • SEMICONDUCTOR DEVICE HAVING A GUARD RING
    Publication number: 20170125356
    Abstract: A semiconductor device includes a semiconductor die having a guard ring disposed in a periphery of the semiconductor die. The semiconductor device also includes a conductive pad over the guard ring. the semiconductor device further has a passivation partially covering the conductive pad, and including a recess to expose a portion of the conductive pad and a post passivation interconnect (PPI) over the passivation. In the semiconductor device, a conductor is extended upwardly from the recess and connected to a portion of the PPI.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Inventors: CHING-FENG YANG, CHUN-LIN LU, KAI-CHIANG WU, VINCENT CHEN
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20170110412
    Abstract: A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package. The semiconductor device further has an EMI (Electromagnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package.
    Type: Application
    Filed: October 19, 2015
    Publication date: April 20, 2017
    Inventors: CHUEI-TANG WANG, VINCENT CHEN, TZU-CHUN TANG, CHEN-HUA YU, CHING-FENG YANG, MING-KAI LIU, YEN-PING WANG, KAI-CHIANG WU, SHOU ZEN CHANG, WEI-TING LIN, CHUN-LIN LU
  • Package alignment structure and method of forming same
    Patent number: 9627325
    Abstract: An embodiment is a semiconductor device comprising a first bond pad on a first substrate, the first bond pad having a first center line through a center of the first bond pad and orthogonal to a top surface of the first substrate, and a first conductive connector on a second substrate, the first conductive connector having a second center line through a center of the first conductive connector and orthogonal to a top surface of the second substrate, the second substrate over the first substrate with the top surface of the first substrate facing the top surface of the second substrate. The semiconductor device further comprises a first alignment component adjacent the first bond pad on the first substrate, the first alignment component configured to align the first center line with the second center line.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Kai Liu, Chia-Chun Miao, Kai-Chiang Wu, Shih-Wei Liang, Ching-Feng Yang, Yen-Ping Wang, Chun-Lin Lu
  • Semiconductor Structure and Manufacturing Method Thereof
    Publication number: 20170098640
    Abstract: A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device.
    Type: Application
    Filed: December 15, 2016
    Publication date: April 6, 2017
    Inventors: Shih-Wei Liang, Hsin-Yu Pan, Kai-Chiang Wu, Ching-Feng Yang, Ming-Kai Liu, Chia-Chun Miao
  • Semiconductor structure and manufacturing method thereof
    Patent number: 9601439
    Abstract: A semiconductor structure includes a substrate, a die disposed over the substrate, and including a die pad disposed over the die and a seal ring disposed at a periphery of the die and electrically connected with the die pad, a polymeric layer disposed over the die, a via extending through the polymeric layer and electrically connected with the die pad, and a molding disposed over the substrate and surrounding the die and the polymeric layer, wherein the seal ring is configured for grounding.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: March 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tzu-Chun Tang, Shou Zen Chang, Wei-Ting Chen, In-Tsang Lin, Vincent Chen, Chuei-Tang Wang, Kai-Chiang Wu, Chun-Lin Lu
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20170062360
    Abstract: A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package. The semiconductor device further has an EMI (Electric Magnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package.
    Type: Application
    Filed: August 28, 2015
    Publication date: March 2, 2017
    Inventors: SHOU ZEN CHANG, CHUN-LIN LU, KAI-CHIANG WU, CHING-FENG YANG, VINCENT CHEN, CHUEI-TANG WANG, YEN-PING WANG, HSIEN-WEI CHEN, WEI-TING LIN
  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20170062353
    Abstract: A semiconductor structure includes a substrate, a die disposed over the substrate, and including a die pad disposed over the die and a seal ring disposed at a periphery of the die and electrically connected with the die pad, a polymeric layer disposed over the die, a via extending through the polymeric layer and electrically connected with the die pad, and a molding disposed over the substrate and surrounding the die and the polymeric layer, wherein the seal ring is configured for grounding.
    Type: Application
    Filed: August 31, 2015
    Publication date: March 2, 2017
    Inventors: TZU-CHUN TANG, SHOU ZEN CHANG, WEI-TING CHEN, IN-TSANG LIN, VINCENT CHEN, CHUEI-TANG WANG, KAI-CHIANG WU, CHUN-LIN LU
  • SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF
    Publication number: 20170062369
    Abstract: The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.
    Type: Application
    Filed: November 10, 2016
    Publication date: March 2, 2017
    Inventors: CHAO-WEN SHIH, KAI-CHIANG WU, CHING-FENG YANG, MING-KAI LIU, SHIH-WEI LIANG, YEN-PING WANG
  • Semiconductor devices and methods of manufacture thereof
    Patent number: 9576874
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads may be arranged in a ball grid array (BGA), and the may include a plurality of corners. A metal dam is disposed around each of the plurality of corners, such as corners of the BGA.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Feng Chen, Kai-Chiang Wu, Chun-Lin Lu, Hung-Jui Kuo
  • Methods and Apparatus for Package with Interposers
    Publication number: 20170047261
    Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.
    Type: Application
    Filed: October 26, 2016
    Publication date: February 16, 2017
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang
  • Methods and Apparatus of Packaging Semiconductor Devices
    Publication number: 20170040269
    Abstract: Methods and apparatus are disclosed which reduce the stress concentration at the redistribution layers (RDLs) of a package device. A package device may comprise a seed layer above a passivation layer, covering an opening of the passivation layer, and covering and in contact with a contact pad. A RDL is formed above the passivation layer, above and in contact with the seed layer, covering the opening of the passivation layer, and electrically connected to the contact pad through the seed layer. The RDL has an end portion with a surface that is smooth without a right angle. The surface of the end portion of the RDL may have an obtuse angle, or a curved surface.
    Type: Application
    Filed: October 19, 2016
    Publication date: February 9, 2017
    Inventors: Chun-Lin Lu, Hsien-Wei Chen, Kai-Chiang Wu, Hung-Jui Kuo