Patents by Inventor Kai-Chiang Wu

Kai-Chiang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Package structure and method for manufacturing thereof
    Patent number: 10163854
    Abstract: A package structure includes a package, at least one second molding material, and at least one electronic component. The package includes at least one first semiconductor device therein, a first molding material, at least one dielectric layer and at least one redistribution line. The first molding material is at least in contact with at least one sidewall of the first semiconductor device. The dielectric layer is over the first semiconductor device and the first molding material. The redistribution line is present at least partially in the dielectric layer and is electrically connected to the first semiconductor device. The second molding material is present on the package. The electronic component is present on the package and is external to the second molding material.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chuei-Tang Wang, Kai-Chiang Wu, Chieh-Yen Chen, Yen-Ping Wang, Shou-Zen Chang
  • Integrated fan-out package and method of fabricating the same
    Patent number: 10163824
    Abstract: An integrated fan-out package including an insulating encapsulation, a radio frequency integrated circuit (RF-IC), an antenna, a ground conductor, and a redistribution circuit structure is provided. The integrated circuit includes a plurality of conductive terminals. The RF-IC, the antenna, and the ground conductor are embedded in the insulating encapsulation. The ground conductor is between the RF-IC and the antenna. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals, the antenna, and the ground conductor. A method of fabricating the integrated fan-out package is also provided.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shou-Zen Chang, Chung-Hao Tsai, Chuei-Tang Wang, Kai-Chiang Wu, Ming-Kai Liu
  • Mechanisms for forming hybrid bonding structures with elongated bumps
    Patent number: 10163846
    Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Ming-Kai Liu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang, Chia-Chun Miao, Hung-Jen Lin
  • INTEGRATED FAN-OUT PACKAGE HAVING MULTI-BAND ANTENNA AND METHOD OF FORMING THE SAME
    Publication number: 20180366347
    Abstract: An integrated fan-out package having a multi-band antenna and a method of forming the same are disclosed. An integrated fan-out package includes a semiconductor die, a molding layer and a plurality of through integrated fan-out vias. The molding layer is aside the semiconductor die. The through integrated fan-out vias are through the molding layer and arranged to form a plurality of dipole antennas. At least one of the plurality of dipole antennas includes two dipole arms each having a transmitting strip and a radiating strip connected to the transmitting part, and the radiating strip has a first part, a second part and a filter part between and in contact with the first part and the second part. The cross-sectional area of the filter part is less than the cross-sectional area of the first part or the second part of the radiating strip.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 20, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nan-Chin Chuang, Ching-Feng Yang, Kai-Chiang Wu
  • Semiconductor device structure
    Patent number: 10157859
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device. The semiconductor device structure includes a conductive element over the first device. The semiconductor device structure includes a first conductive shielding layer between the first device and the conductive element. The first conductive shielding layer has openings, and a maximum width of the opening is less than a wavelength of an energy generated by the first device. The semiconductor device structure includes a second conductive shielding layer under the first device. The first device is between the first conductive shielding layer and the second conductive shielding layer, and the second conductive shielding layer has a plurality of second openings.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shou-Zen Chang, Chi-Ming Huang, Kai-Chiang Wu, Sen-Kuei Hsu, Hsin-Yu Pan, Han-Ping Pu, Albert Wan
  • Semiconductor structure and manufacturing method thereof
    Patent number: 10157900
    Abstract: A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Liang, Hsin-Yu Pan, Kai-Chiang Wu, Ching-Feng Yang, Ming-Kai Liu, Chia-Chun Miao
  • Method of packaging semiconductor devices
    Patent number: 10153240
    Abstract: Methods and apparatus are disclosed which reduce the stress concentration at the redistribution layers (RDLs) of a package device. A package device may comprise a seed layer above a passivation layer, covering an opening of the passivation layer, and covering and in contact with a contact pad. A RDL is formed above the passivation layer, above and in contact with the seed layer, covering the opening of the passivation layer, and electrically connected to the contact pad through the seed layer. The RDL has an end portion with a surface that is smooth without a right angle. The surface of the end portion of the RDL may have an obtuse angle, or a curved surface.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: December 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Lin Lu, Hsien-Wei Chen, Kai-Chiang Wu, Hung-Jui Kuo
  • Packaged Semiconductor Devices and Packaging Methods
    Publication number: 20180350771
    Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a first molding material disposed around the integrated circuit die, and a through-via disposed within the first molding material. A first side of a redistribution layer (RDL) is coupled to the integrated circuit die, the through-via, and the first molding material. A second molding material is over a second side of the RDL, the second side of the RDL being opposite the first side of the RDL. The packaged semiconductor device includes an antenna over the second molding material.
    Type: Application
    Filed: August 13, 2018
    Publication date: December 6, 2018
    Inventors: Tzu-Chun Tang, Chuei-Tang Wang, Chun-Lin Lu, Wei-Ting Chen, Vincent Chen, Shou-Zen Chang, Kai-Chiang Wu
  • SEMICONDUCTOR DEVICE
    Publication number: 20180350752
    Abstract: A semiconductor device includes a semiconductor die, an insulative layer, a plurality of conductive features, a dummy redistribution layer (RDL), and an Electromagnetic Interference (EMI) shield. The insulative layer covers the semiconductor die. The conductive features substantially surround the insulative layer. The dummy RDL is over the insulative layer and electrically disconnected from the semiconductor die. The EMI shield is in contact with the plurality of conductive features and the dummy RDL.
    Type: Application
    Filed: August 6, 2018
    Publication date: December 6, 2018
    Inventors: CHUEI-TANG WANG, VINCENT CHEN, TZU-CHUN TANG, CHEN-HUA YU, CHING-FENG YANG, MING-KAI LIU, YEN-PING WANG, KAI-CHIANG WU, SHOU ZEN CHANG, WEI-TING LIN, CHUN-LIN LU
  • Solder Ball Protection in Packages
    Publication number: 20180337144
    Abstract: An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Chia-Chun Miao, Shih-Wei Liang, Kai-Chiang Wu
  • MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE
    Publication number: 20180308817
    Abstract: A method for forming a semiconductor structure includes: providing a semiconductor substrate having a first pad and a second pad on a top surface of the semiconductor substrate; providing a circuit board having an active pad and a non-metallic surface; providing a first solder ball and a second solder ball on the active pad and the non-metallic surface respectively; attaching the first pad and the second pad on the first solder ball and the second solder ball respectively; and reflowing the first solder ball and the second solder ball to form a first bump wetted on the active pad and a second bump not wetted on the non-metallic surface.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 25, 2018
    Inventors: CHUN-LIN LU, KAI-CHIANG WU
  • Polymer layers embedded with metal pads for heat dissipation
    Patent number: 10109605
    Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Hsiang Chuang, Shih-Wei Liang, Ching-Feng Yang, Kai-Chiang Wu, Hao-Yi Tsai, Chuei-Tang Wang, Chen-Hua Yu
  • Packaging devices and methods
    Patent number: 10079200
    Abstract: A method of manufacturing a packaging device may include: forming a plurality of through-substrate vias (TSVs) in a substrate, wherein each of the plurality of TSVs has a protruding portion extending away from a major surface of the substrate. A seed layer may be forming over the protruding portions of the plurality of TSVs, and a conductive ball may be coupled to the seed layer and the protruding portion of each of the plurality of TSVs. The seed layer and the protruding portion of each of the plurality of TSVs may extend into an interior region of the conductive ball.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: September 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shih-Wei Liang, Kai-Chiang Wu, Ming-Che Ho, Yi-Wen Wu
  • Integrated Devices in Semiconductor Packages and Methods of Forming Same
    Publication number: 20180247905
    Abstract: An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.
    Type: Application
    Filed: October 5, 2017
    Publication date: August 30, 2018
    Inventors: Chen-Hua Yu, Kai-Chiang Wu, Chung-Shi Liu, Shou Zen Chang, Chao-Wen Shih
  • Methods and Apparatus for Package with Interposers
    Publication number: 20180240723
    Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.
    Type: Application
    Filed: April 20, 2018
    Publication date: August 23, 2018
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang
  • MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE
    Publication number: 20180233472
    Abstract: The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.
    Type: Application
    Filed: April 12, 2018
    Publication date: August 16, 2018
    Inventors: CHAO-WEN SHIH, KAI-CHIANG WU, CHING-FENG YANG, MING-KAI LIU, SHIH-WEI LIANG, YEN-PING WANG
  • Solder ball protection in packages
    Patent number: 10049990
    Abstract: An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chun Miao, Shih-Wei Liang, Kai-Chiang Wu
  • Packaged semiconductor devices and packaging methods
    Patent number: 10050013
    Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a first molding material disposed around the integrated circuit die, and a through-via disposed within the first molding material. A first side of a redistribution layer (RDL) is coupled to the integrated circuit die, the through-via, and the first molding material. A second molding material is over a second side of the RDL, the second side of the RDL being opposite the first side of the RDL. The packaged semiconductor device includes an antenna over the second molding material.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Chun Tang, Chuei-Tang Wang, Chun-Lin Lu, Wei-Ting Chen, Vincent Chen, Shou-Zen Chang, Kai-Chiang Wu
  • Semiconductor device and manufacturing method thereof
    Patent number: 10043761
    Abstract: A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package. The semiconductor device further has an EMI (Electromagnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: August 7, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chuei-Tang Wang, Vincent Chen, Tzu-Chun Tang, Chen-Hua Yu, Ching-Feng Yang, Ming-Kai Liu, Yen-Ping Wang, Kai-Chiang Wu, Shou Zen Chang, Wei-Ting Lin, Chun-Lin Lu
  • Semiconductor structure and manufacturing method thereof
    Patent number: 10037959
    Abstract: A semiconductor structure includes a conductive bump, and a ferromagnetic member extended within the conductive bump, wherein a center of the conductive bump is disposed on a central axis of the ferromagnetic member.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: July 31, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Chun Miao, Shih-Wei Liang, Yen-Ping Wang, Kai-Chiang Wu, Ming-Kai Liu