Patents by Inventor Kai-Chiang Wu

Kai-Chiang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for singulating packaged integrated circuits and resulting structures
    Patent number: 10964595
    Abstract: A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through the molding compound and a top portion of the wafer using a beveled saw blade, while leaving a bottom portion of the wafer remaining. The method further includes sawing through the bottom portion of the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the beveled saw blade. The resulting structure is within the scope of the present disclosure.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Ping Wang, Ming-Kai Liu, Kai-Chiang Wu
  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210091031
    Abstract: A semiconductor structure includes a semiconductor substrate; a first pad and a second pad on a first top surface of the semiconductor substrate; a circuit board including a second top surface, a recess indented from the second top surface into the circuit board, a polymeric pad disposed on the second top surface and corresponding to the first pad, and an active pad disposed within the recess and corresponding to the second pad; a first bump disposed between and contacting the polymeric pad and the first pad; and a second bump disposed between and contacting the active pad and the second pad, wherein a height of the first bump is substantially shorter than a height of the second bump.
    Type: Application
    Filed: December 8, 2020
    Publication date: March 25, 2021
    Inventors: CHUN-LIN LU, KAI-CHIANG WU
  • EMI shielding structure in InFO package
    Patent number: 10950556
    Abstract: A method includes forming a metal post over a first dielectric layer, attaching a second dielectric layer over the first dielectric layer, encapsulating a device die, the second dielectric layer, a shielding structure, and the metal post in an encapsulating material, planarizing the encapsulating material to reveal the device die, the shielding structure, and the metal post, and forming an antenna electrically coupling to the device die. The antenna has a portion vertically aligned to a portion of the device die.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chiang Wu, Chen-Hua Yu, Ching-Feng Yang, Meng-Tse Chen
  • PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20210020560
    Abstract: A package structure includes a first RDL structure, a die, an encapsulant, a film, a TIV and a second RDL structure. The die is located over the first RDL structure. The encapsulant laterally encapsulates sidewalls of the die. The film is disposed between the die and the first RDL structure, and between the encapsulant and the first RDL structure. The TIV penetrates through the encapsulant and the film to connect to the first RDL structure. The second RDL structure is disposed on the die, the TIV and the encapsulant and electrically connected to die and the TIV.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuei-Tang Wang, Chun-Lin Lu, Kai-Chiang Wu
  • SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210020559
    Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a semiconductor die, a through via structure, a dipole structure and an encapsulant. The through via structure and the dipole structure are disposed aside the semiconductor die, and respectively includes an insulating core and a conductive layer. A front surface and a sidewall of the insulating core are covered by the conductive layer. The semiconductor die, the through via structure and the dipole structure are laterally encapsulated by the encapsulant. Surfaces of capping portions of the conductive layers covering the front surfaces of the insulating cores are substantially coplanar with a front surface of the encapsulant.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tuan-Yu Hung, Ching-Feng Yang, Hung-Jui Kuo, Kai-Chiang Wu, Ming-Che Ho
  • PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210013151
    Abstract: A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 14, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu
  • Electronic device and manufacturing method thereof
    Patent number: 10868353
    Abstract: An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, an antenna pattern, and an insulating layer. The chip package includes a semiconductor die and an insulating encapsulation enclosing the semiconductor die. The antenna pattern is electrically coupled to the chip package, where a material of the antenna pattern comprises a conductive powder having fused metal particles. The insulating layer disposed between the chip package and the antenna pattern, where the antenna pattern includes a first surface in contact with the insulating layer, and a second surface opposite to the first surface, and a surface roughness of the second surface is greater than a surface roughness of the first surface.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Lin Lu, Hsiu-Jen Lin, Hsuan-Ting Kuo, Kai-Chiang Wu, Ming-Che Ho, Wei-Yu Chen, Yu-Peng Tsai, Chia-Lun Chang, Chia-Shen Cheng, Chih-Chiang Tsao, Tzu-Chun Tang, Ching-Hua Hsieh, Tuan-Yu Hung, Cheng-Shiuan Wong
  • Mechanisms for forming hybrid bonding structures with elongated bumps
    Patent number: 10867957
    Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Ming-Kai Liu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang, Chia-Chun Miao, Hung-Jen Lin
  • Semiconductor structure and manufacturing method thereof
    Patent number: 10867952
    Abstract: A semiconductor structure includes a semiconductor substrate; a first pad and a second pad on a top surface of the semiconductor substrate; a circuit board including a polymeric pad and an active pad corresponding to the first pad and the second pad on the top surface of the semiconductor substrate respectively; a first bump disposed between the polymeric pad and the first pad; and a second bump disposed between the active pad and the second pad; wherein a first thickness of the polymeric pad is greater than a second thickness of the active pad. Further, a method of manufacturing the semiconductor structure is disclosed. The method includes providing a circuit board; and forming a polymeric pad and an active pad on a surface of the circuit board, wherein a first thickness of the polymeric pad is substantially greater than a second thickness of the active pad.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Lin Lu, Kai-Chiang Wu
  • SEMICONDUCTOR PACKAGES HAVING THERMAL THROUGH VIAS (TTV)
    Publication number: 20200373219
    Abstract: A semiconductor package includes a die, a dummy die, a plurality of conductive terminals, an insulating layer and a plurality of thermal through vias. The dummy die is disposed aside the die. The conductive terminals are disposed at a first side of the dummy die and the die and electrically connected to the dummy die and the die. The insulating layer is disposed at a second side opposite to the first side of the dummy die and the die. The thermal through vias penetrating through the insulating layer.
    Type: Application
    Filed: August 14, 2020
    Publication date: November 26, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sen-Kuei Hsu, Ching-Feng Yang, Hsin-Yu Pan, Kai-Chiang Wu, Yi-Che Chiang
  • INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20200373173
    Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and at least one first through interlayer via. The first redistribution structure includes a dielectric layer, a feed line at least partially disposed on the dielectric layer and a signal enhancement layer covering the feed line, wherein the signal enhancement layer has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The at least one first TIV is embedded in the insulation encapsulation and the signal enhancement layer.
    Type: Application
    Filed: August 11, 2020
    Publication date: November 26, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Chiang Wu, Chung-Hao Tsai, Chun-Lin Lu, Yen-Ping Wang, Che-Wei Hsu
  • MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE
    Publication number: 20200357659
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor die and surrounding a sidewall of the semiconductor die with a dielectric material. The method further includes forming a post passivation interconnect (PPI) over the semiconductor die and electrically coupling the PPI with the semiconductor die. The method further includes molding the semiconductor die and the PPI into an integrated semiconductor package. The method further includes covering at least a portion of an outer surface of the integrated semiconductor package with a conductive layer, wherein the conductive layer is conformal to the morphology of the portion of the outer surface. Moreover, the method further includes forming a conductive path inside the integrated semiconductor package electrically coupled to the conductive layer and a ground terminal of the integrated semiconductor package.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: SHOU ZEN CHANG, CHUN-LIN LU, KAI-CHIANG WU, CHING-FENG YANG, VINCENT CHEN, CHUEI-TANG WANG, YEN-PING WANG, HSIEN-WEI CHEN, WEI-TING LIN
  • Package structure with reinforcement structures in a redistribution circuit structure and method of manufacturing the same
    Patent number: 10825773
    Abstract: A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu
  • PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20200343203
    Abstract: A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation. A method of manufacturing a package structure is also provided.
    Type: Application
    Filed: July 8, 2020
    Publication date: October 29, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Chiang Wu, Han-Ping Pu, Yen-Ping Wang
  • MANUFACTURING METHOD OF SEMICONDCUTOR PACKAGE
    Publication number: 20200303331
    Abstract: A method including followings is provided. An encapsulated device including a semiconductor die and an insulating encapsulation laterally encapsulating the semiconductor die is provided. An insulating layer is formed over a surface of the encapsulated device. A groove pattern is formed on the insulating layer. A conductive paste is filled in the groove pattern and the conductive paste filled in the groove pattern is cured.
    Type: Application
    Filed: June 4, 2020
    Publication date: September 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fang-Yu Liang, Ching-Feng Yang, Kai-Chiang Wu
  • PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20200294926
    Abstract: A package structure and the method thereof are provided. The package structure includes a conductive plate, a semiconductor die, a molding compound, and antenna elements. The conductive plate has a first surface, a second surface and a sidewall connecting the first surface and the second surface. The semiconductor die is located on the second surface of the conductive plate. The molding compound laterally encapsulates the semiconductor die and covers the sidewall and a portion of the second surface exposed by the semiconductor die, wherein the first surface of the conductive plate is coplanar with a surface of the molding compound. The antenna elements are located over the first surface of the conductive plate.
    Type: Application
    Filed: June 3, 2020
    Publication date: September 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Chiang Wu, Chen-Hua Yu, Kuo-Chung Yee
  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20200286846
    Abstract: A semiconductor structure includes a semiconductor substrate; a first pad and a second pad on a top surface of the semiconductor substrate; a circuit board including a polymeric pad and an active pad corresponding to the first pad and the second pad on the top surface of the semiconductor substrate respectively; a first bump disposed between the polymeric pad and the first pad; and a second bump disposed between the active pad and the second pad; wherein a first thickness of the polymeric pad is greater than a second thickness of the active pad.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: CHUN-LIN LU, KAI-CHIANG WU
  • PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20200286825
    Abstract: A package structure includes a redistribution circuit structure, at least one semiconductor die, an insulating encapsulation, insulators, and metallic patterns. The at least one semiconductor die is located on and electrically connected to the redistribution circuit structure. The insulating encapsulation encapsulates the at least one semiconductor die and located on the redistribution circuit structure. The insulators are located on the redistribution circuit structure, wherein the insulators are separated and spaced apart from each other, wherein edges of each of the insulators are distant from edges of the at least one semiconductor die by an offset in a stacking direction of the redistribution circuit structure and the insulating encapsulation. Each of the metallic patterns is located on a respective one of the insulators.
    Type: Application
    Filed: May 24, 2020
    Publication date: September 10, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Ling Hwang, Chun-Lin Lu, Kai-Chiang Wu
  • Integrated fan-out package and manufacturing method thereof
    Patent number: 10770313
    Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and a second redistribution structure. The first redistribution structure has a dielectric layer and a feed line disposed on the dielectric layer. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The insulation encapsulation has a protrusion laterally wraps around the feed line. The insulation encapsulation has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer. The second redistribution structure is disposed on the die and the insulation encapsulation.
    Type: Grant
    Filed: April 21, 2019
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Chiang Wu, Chung-Hao Tsai, Chun-Lin Lu, Yen-Ping Wang, Che-Wei Hsu
  • Package structure and manufacturing method thereof
    Patent number: 10748861
    Abstract: A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Chiang Wu, Han-Ping Pu, Yen-Ping Wang